Vector data processing system with instruction synchronization

An information processing system, comprising:

• main storage means for storing data and application program instructions including sequentially arranged scalar instructions and vector instructions having a synchronization instruction therein where the synchronization instruction is for synchronizing parallel instruction processing of the scalar and vector instructions and said main storage means for generating a storage completion signal when a storage operation is complete;
• instruction controller means, connected to said main storage means, for sequentially fetching the scalar and vector instructions from said main storage means, for separately outputting the scalar and vector instructions, for generating operation end information in dependence upon the vector instructions when a related group of application program instructions have been output and for inhibiting the outputting of the scalar and vector instructions;
• scalar arithmetic means, connected to said main storage means and said instruction controller means, for receiving the scalar instructions and processing the data stored in said main storage means in dependence upon the scalar instructions, for generating a scalar instruction finish inhibit signal during execution of the scalar instructions containing the synchronization instruction and for generating a scalar instruction end signal when the scalar instructions containing the synchronization instruction have finished executing;
• and
• vector arithmetic means, connected to said main storage means and said instruction controller means, for receiving the vector instructions and for processing the data stored in said main storage means in dependence upon the vector instructions, said vector arithmetic means comprising:
• an instruction register, connected to said instruction controller means, for storing and passing therethrough the vector instructions and for generating a first empty signal when said instruction register is empty;
• pipe line processor means, connected to said instruction register and said main storage means, having pipe line processors, for decoding the vector instructions, for processing the data stored in said main storage means in dependence upon the vector instructions and for generating a process finished signal when the processing is finished, said pipe line processor means includes an identification register and said vector instructions have an identification number and include a serialized starting instruction and a serialized releasing instruction for synchronizing the vector instructions distributed to different pipe line processors;
• an instruction buffer, connected to said instruction register and said pipe line processor means, for storing and passing therethrough vector instructions, for generating a buffer full signal when said instruction buffer is full and for generating a second empty signal when said instruction buffer is empty;
• an operation end receiver, connected to said instruction controller means, for receiving the operation end information and for generating an operation end signal;
• an instruction finish detecting circuit, connected to said main storage means, said pipe line processor means, said instruction register and said instruction buffer, for generating a vector instruction end signal in dependence upon the first empty signal, the second empty signal, the process finished signal and the storage completion signal;
• wait instruction detecting means, connected to said instruction register and said instruction finish detecting circuit, for generating a wait signal in dependence upon the synchronization instruction and the instruction end signal;
• a control register, connected to said instruction register, for storing a parallel/serial indicator indicating a parallel or a serial processing mode;
• inhibit means, connected to said instruction controller means, said control register, said operation end receiver, said instruction buffer, said wait instruction detecting means and said instruction finish detecting circuit, for generating a vector instruction finish inhibit signal in dependence upon the parallel/serial indicator, the operation end signal, the buffer full signal, the wait signal and the instruction end signal, said instruction controller means being inhibited from transferring vector instructions to said vector arithmetic means by the vector instruction finish inhibit signal;
• an instruction holding register connected to said instruction register and said pipe line processor means;
• and
• an instruction dispatch controller, connected to said instruction register, said instruction holding register and said identification register, for assigning an identification number to said pipe line processor means, for storing the identification number from said serialized starting instruction in said pipe line processor means, for transferring to said pipe line processor means only those vector instructions with the identification number and for temporarily storing an instruction located sequentially after the serialized releasing instruction in said instruction holding register until said pipe line processor means is available, said instruction controller means inhibiting outputting of scalar and vector instructions when the vector instruction finish signal or the scalar instruction finish inhibit signal is received and allowing outputting of scalar and vector instructions after an inhibition when the vector instruction end signal and the scalar instruction end signal have both been received, so that the related group of application program instructions are all processed before a next related group of application program instructions is processed.