Digital processor capable of concurrently executing external memory access and internal instructions

A digital processor for implementing an instruction to transfer continuously a stream of data to an external memory, said digital processor comprising:

• an instruction memory;
• a sequencer for reading instructions from said instruction memory;
• a decoder for analyzing said instructions, incorporated on a semiconductor chip and being capable of executing a stream of data continuous transfer instruction for an external memory;
• and
• an external memory reference control circuit comprising:
• a first storage means for fetching a stream of data continuous transfer signal being output from said decoder;
• a second storage means for fetching an operand of said stream of data continuous transfer instruction;
• a selection means for holding said operand in said second storage means;
• a cycle control circuit for controlling an external memory associated with said digital processor and internal resources of said digital processor;
• and
• a synchronous control circuit for providing a start signal to said cycle control circuit and for providing a holding signal for controlling said selection means and a reset signal for resetting said second storage means when said synchronous control circuit senses termination of said stream of data continuous transfer instruction by receiving a termination signal;
• said sequencer serving to keep later instructions being read while said stream of data continuous transfer instruction is being executed and to execute the later instructions concurrently with said stream of data continuous transfer instruction if said later instructions are an instruction group for referring to resources unoccupied by said stream of data continuous transfer instruction.

A digital processor, comprising:

• (a) an instruction memory for storing instructions including an external memory reference instruction and other instructions;
• (b) a sequencer for receiving a first clock signal and reading said instructions from said instruction memory in response to said first clock signal;
• (c) a decoder for analyzing said instructions to output instruction signals including an external memory reference instruction signal representing said external memory reference instruction and other instruction signals representing said other instructions;
• (d) an operation block comprising executing means for executing at least some of said external memory reference instruction and said other instructions in response to the first clock signal;
• and
• (e) an external memory reference control circuit for receiving a second clock signal and controlling reference to an external memory in response to said second clock signal and said external memory reference instruction signal;
• said external memory reference control circuit including:
• (i) a first storage means responsive to the first clock signal for fetching and storing said external memory reference instruction signal output from said decoder;
• (ii) a second storage means responsive to the first clock signal for fetching and storing an operand of said external memory reference instruction;
• (iii) a selection means for holding said operand in said second storage means;
• (iv) a cycle control circuit for controlling said external memory and said operation block;
• and
• (v) a synchronous control circuit, synchronized with the first clock signal and the second clock signal, for providing a start signal to said cycle control circuit, and for providing a holding signal for controlling said selection means and a reset signal for resetting said second storage means when said synchronous control circuit senses a termination of execution of said external memory reference instruction upon receipt of a termination signal from said cycle control circuit, wherein:
• when said external memory reference instruction is read out from said instruction memory by said sequencer, the external memory reference instruction signal and said operand are fetched and stored by said first and second storage means respectively, said sequencer continues to read out said other instructions from said instruction memory even while said external memory reference instruction is being executed, and said selection means controls said second storage means to hold said operand until a termination of an external memory cycle executed by said external memory reference instruction and to release said operand upon termination of the external memory cycle, and
• when said other instructions are instructions which use resources unoccupied by said external memory reference instruction, said other instructions are executed in parallel with said external memory reference instruction.

A digital processor for executing an instruction for continuously transferring a stream of data between said digital processor and an external memory, said digital processor comprising:

• (a) an instruction memory for storing instructions including said instruction for continuously transferring said stream of data between said digital processor and said external memory and other instructions;
• (b) a sequencer for receiving a first clock signal and reading said instruction for continuously transferring said stream of data and said other instructions from said instruction memory in response to the first clock signal;
• (c) a decoder for analyzing said instruction for continuously transferring said stream of data and said other instructions to output instruction signals including a signal indicating said instruction for continuously transferring said stream of data and other instruction signals representing said other instructions;
• (d) an operation block comprising executing means for executing at least some of said instruction for continuously transferring said stream of data and said other instructions in response to the first clock signal;
• and
• (e) an external memory reference control circuit for receiving a second clock signal and controlling reference to the external memory in response to the second clock signal and said signal indicating said instruction for continuously transferring said stream of data;
• said external memory reference control circuit including:
• (i) a first storage means responsive to the first clock signal for fetching and storing said signal indicating said instruction for continuously transferring the stream of data outputted from said decoder;
• (ii) a second storage means responsive to the first clock signal for fetching and storing an operand of said instruction for continuously transferring the stream of data;
• (iii) a selection means for holding said operand in said second storage means;
• (iv) a cycle control circuit for controlling said external memory and the operation block;
• and
• (v) a synchronous control circuit, synchronized with the first clock signal and the second clock signal, for providing a start signal to said cycle control circuit, and for providing a holding signal for controlling said selection means and a reset signal for resetting said second storage means when said synchronous control circuit senses a termination of execution of said instruction for continuously transferring the stream of data upon receipt of a termination signal from said cycle control circuit, wherein:
• when said instruction for continuously transferring the stream of data is read out from said instruction memory by said sequencer, the signal indicating said instruction for continuously transferring the stream of data and said operand are fetched and stored by said first and second storage means respectively, said sequencer continues to read out said other instructions from said instruction memory even while said instruction for continuously transferring the stream of data is executed, and said selection means controls said second storage means to hold said operand until termination of an external memory cycle executed by said instruction for continuously transferring the stream of data and to release said operand upon termination of the external memory cycle, and
• when said other instructions are instructions which use resources unoccupied by said instruction for continuously transferring the stream of data, said other instructions are executed in parallel with said instruction for continuously transferring the stream of data.