Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus

A parity error detection and recovery mechanism for use in a computer system which comprises (i) a system bus having connected thereto a central processing unit (CPU);

• (ii) a peripheral bus having connected thereto a master peripheral device which initiates transactions over said peripheral bus in which data is transferred between said master peripheral device and a slave peripheral device connected to said peripheral bus, said master peripheral device able to detect parity errors occurring during said transactions and re-initiate a transaction if a parity error is detected;
• and (iii) a host bridge connecting said system bus to a peripheral bus for simultaneously monitoring said transactions as they occur over said peripheral bus;
• said parity error detection and recovery mechanism comprising:
• a status register which is set by said master peripheral device upon detection of a parity error occurring during a transaction, and which is reset by said master peripheral device if a re-initiated transaction is successfully transacted without an occurrence of a parity error;
• register space in said host bridge for temporarily storing the identification of a master peripheral device initiating a transaction and said data being transmitted over said peripheral bus between said master peripheral device and said slave peripheral device during the transaction;
• and
• logic for saving said data and identification information in said host bridge register space and generating an interrupt routine over said system bus to said CPU, in response to detection of a parity error over said peripheral bus, wherein said CPU gains access to said peripheral bus in response to said interrupt routine and alternatively (a) reads said register space in said host bridge and attempts recovery operations over said peripheral bus if said status bit is set or (b) relinquishes control of said peripheral bus if said status bit is not set, indicating that a re-initiated transaction has been successfully transacted by said master peripheral device without an occurrence of a parity error.

A method of detecting and recovering from parity errors in a computer system which comprises (i) a system bus having connected thereto a central processing unit (CPU);

• (ii) a peripheral bus having connected thereto a master peripheral device which initiates transactions over said peripheral bus in which data is transferred between said master peripheral device and a slave peripheral device connected to said peripheral bus, said master peripheral device able to detect parity errors occurring during said transactions and re-initiate a transaction if a parity error is detected;
• and (iii) a host bridge connecting said system bus to a peripheral bus for simultaneously monitoring said transactions as they occur over said peripheral bus;
• said method comprising the steps of:
• temporarily storing in register space in said host bridge the identification of a master peripheral device initiating a transaction and said data being transmitted over said peripheral bus between said master peripheral device and said slave peripheral device during the transaction;
• detecting a parity error in the transaction;
• setting a status register with said master peripheral device which has initiated the transaction in response to the detection of a parity error;
• generating an interrupt routine over said system bus to said CPU;
• allowing said CPU to gain access to said peripheral bus in response to said interrupt routine;
• and
• alternatively (a) reading said register space in said host bridge and attempting recovery operations over said peripheral bus by said CPU if said status bit is set or (b) relinquishing control of said peripheral bus by said CPU if said status bit is not set, indicating that a re-initiated transaction has been successfully transacted by said master peripheral device without an occurrence of a parity error.