Bus arbitration system

#The present invention relates to a data processing apparatus and, more particularly, to a bus arbitration system for a data processing apparatus to which a plurality of bus masters of relatively low degrees of priority are connected.

#Conventional bus arbitration systems for the above application are disclosed in, for example, Japanese Patent Application Disclosure No. Sho 62-229353.

#The above document discloses three different conventional systems, i.e., a first system using a daisy chain system, a second system using a priority arbitration system, and a third system using a round robin system. The daisy chain system connects a plurality of bus masters in series and gives the highest priority to the electrically uppermost bus master. The priority arbitration system connects a plurality of bus masters in parallel, inputs to a bus arbiter bus request signals which are outputted by the bus masters in synchronism, and sequentially selects the bus masters according to a predetermined priority order to give them an allowance signal. Further, the round robin system causes a bus arbiter to cyclically scan bus masters to see if any one of them is outputting a bus request signal, give an allowance signal to the bus master outputting a bus request signal on detecting such a bus master, and handles this bus master as a bus master of lowest priority at the time of the next bus arbitration.

#The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which:

#FIG. 1 is a block diagram schematically showing a bus arbitration system embodying the present invention;

#FIG. 2 is a timing chart representative of a specific operation of the embodiment;

#Referring to FIG. 1 of the drawings, a bus arbitration system embodying the present invention has a bus master A 1, a bus masters B 2, a bus master C 3, a counter section 5 for counting each of the duration of bus occupation, i.e., bus occupation times of the bus masters, a bus arbiter section 6 for giving an allowance signal (referred to as a bus ACK signal) to a particular bus master selected on the basis of the bus occupation times from the counter 5 and bus request signals from the bus masters, a counter initialization control section 4 for initializing the counter section 5 every predetermined period of time, and an AND gate 7.

#The counter initialization control 4 is initialized by a power on reset signal 10. As a timer built in the control 4 section counts a predetermined period of time in response to a bus clock 24, the control section 4 generates a counter reset signal 11.

#FIG. 3 shows a specific construction of the counter initialization control 4 section. As shown, the control section 4 is made up of a clock input terminal 31, a reset input terminal 32 for receiving the power on reset signal, a counter reset off signal input terminal 33, a counter reset signal output terminal 34, a 20-bit counter 35 for determining the interval between consecutive resetting of the counter 5, and flip-flops 36 and 37 for controlling the timing for outputting the counter reset signal.