Fractional bit-leaking clock signal resynchronizer for a high-speed digital communications system

A clock signal resynchronizer for use in a high-speed digital communications system, comprising:

• a first circuit operable to receive a periodically discontinuous clock signal and output a first signal indicative of said periodically discontinuous clock signal;
• a filter circuit operable to receive a phase hit adjustment signal at an input and supply a plurality of high-pass filtered output signals, said plurality of high-pass filtered output signals representing, in combination, said phase hit adjustment input signal;
• a summing circuit coupled to said filter circuit and said first circuit, said summing circuit operable to sum each of said plurality of high-pass filtered signals with said first signal and supply a corresponding plurality of summed output signals;
• and
• a phase-locked loop circuit comprising a plurality of phase detector circuits, each phase detector circuit corresponding to one of said plurality of summed output signals, a digital to analog converter circuit operable to convert said summed output signals to an analog control signal, and a controllable frequency signal generator operable to generate said smoothed clock output signal responsive to said analog control signal, said phase-locked loop circuit coupled to said summing circuit and operable to process said plurality of summed output signals to generate a smoothed clock signal output whose frequency is indicative of the sum of said first signal and said plurality of filtered output signals.

A clock signal resynchronizer for use in a high-speed digital communications system, comprising:

• a digital filter circuit including at least a first input, a first output, and a second output complementary to said first output, said complementary first and second outputs indicative of said first input;
• a first summation circuit and a second summation circuit, said first output coupled to an input of said first summation circuit, and said second output coupled to an input of said second summation circuit;
• an elastic buffer circuit including a data input, a write address input, a read address input, and a data output, said elastic buffer operable to store data written in response to a write address provided, and transmit data read out responsive to a read address provided;
• a write counter circuit including an input and output and operable to provide said write address, said output of said write counter circuit coupled to said write address input and a second input of each of said first and second summation circuits;
• a first phase detector circuit and a second phase detector circuit, a first input of each said phase detector circuit coupled to a respective output of said first and second summation circuits, and an output of each said phase detector circuit coupled to a third summation circuit;
• a smoothed clock generator circuit operable to generate a smoothed clock output signal responsive to combined signals received from said third summation circuit;
• and
• a read counter circuit operable to provide said read address, connected between said smoothed clock output and said read address input, and a second input of each of said phase detector circuits.

A method of resynchronizing a clock signal in a high-speed digital communications system, comprising the steps of:

• high-pass filtering phase hit adjustments to produce a first digital signal;
• summing a plurality of higher order bits of said first digital signal and at least a lower order bit of said first digital signal with a periodically discontinuous clock signal;
• phase detecting said summed plurality of higher order bits to produce a first error signal and said summed at least a lower order bit to produce a second error signal;
• summing said first error signal with said second error signal to produce a control signal;
• controlling an oscillator with said control signal to produce a smoothed clock output signal;
• and
• supplying a feedback signal indicative of the frequency of said smoothed clock output signal to be used in said phase detecting step to produce said first error signal and said second error signal.

A method of resynchronizing a clock signal in a high-speed digital communications system, comprising the steps of:

• high-pass filtering a phase hit adjustment to produce a first digital signal and a second digital signal;
• summing said first digital signal with a periodically discontinuous signal to produce a third digital signal, and summing said second digital signal with said periodically discontinuous signal to produce a fourth digital signal;
• and
• low-pass filtering said third and fourth digital signals in a phase-locked loop to generate a periodically continuous fifth signal whose frequency is indicative of the sum of said first and second digital signals and said periodically discontinuous signal.