Method and apparatus for symbol clock recovery from signal having wide frequency possibilities

A method for symbol clock recovery from a received inphase signal and a received quadrature signal having wide frequency possibilities, said method comprising the steps of:

• (a) sampling the received inphase signal at sampling times to provide a sampled inphase signal;
• (b) sampling the received quadrature signal at the sampling rate to provide a sampled quadrature signal;
• (c) determining a first signal indicative of a magnitude of the received inphase signal;
• (d) determining a second signal indicative of a magnitude of the received quadrature signal;
• (e) distributing the first and second signals among a plurality of accumulator registers;
• (f) in the accumulator registers, accumulating sums of the first and second signals for each sample time and substantially over a length of an expected burst;
• (g) determining the accumulator register having one of a largest sum and a smallest sum to provide a recovered clock signal;
• and
• (h) downsampling the sampled inphase signal and sampled quadrature signal based on the recovered clock signal.

An apparatus for symbol clock recovery from a received inphase signal and a received quadrature signal having wide frequency possibilities, said apparatus comprising:

• a first sampler for sampling the received inphase signal at sampling times to provide a sampled inphase signal;
• a second sampler for sampling the received quadrature signal at the sampling rate to provide a sampled quadrature signal;
• a first magnitude determination circuit operatively coupled to said first sampler for receiving the sampled inphase signal to provide a first signal indicative of a square of the received inphase signal;
• a second magnitude determination circuit operatively coupled to said second sampler for receiving the sampled quadrature signal to provide a second signal indicative of a square of the received quadrature signal;
• an adder operatively coupled to said first magnitude determination circuit, said second magnitude determination circuit and said distributor for adding the first and second signals to provide an added signal;
• a distributor operatively coupled to said adder for distributing the added signal;
• a plurality of accumulator registers operatively coupled to said distributor for accumulating sums of the first and second signals for each sample time and substantially over a length of an expected burst, wherein said plurality of accumulator registers consists of a number of registers equal to the number of sample times per symbol of an expected burst;
• a maximum-minimum determination circuit operatively coupled to said plurality of accumulator registers for determining the accumulator register having one of a largest sum and a smallest sum to provide a recovered clock signal;
• and
• a downsampler operatively coupled to said maximum-minimum determination circuit, said first sampler and said second sampler for downsampling the sampled inphase signal and sampled quadrature signal based on the recovered clock signal, wherein said downsampler comprises a carrier recovery stage operatively coupled to said maximum-minimum determination circuit, said first sampler and said second sampler for recovering carrier based on the recovered clock signal, sampled inphase signal and sampled quadrature signal.