US 5,499,249 AGranted

Method and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs)

AssigneeAT&T Corp.

InventorsVishwani D. Agrawal, Tapan J. Chakraborty

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Abstract

Testing of a sequential circuit (10) containing at least one embedded RAM (16) is accomplished by first generating a set of sequential vectors and then applying the vectors in sequence to a set of primary circuit inputs (PO.sub.o -PO.sub.j). The vectors are generated such that upon application to the circuit, the vectors excite potential faults at nodes (A) upstream of the RAM and propagate the effects of the faults through the RAM to the primary circuit outputs (PO.sub.o -PO.sub.j). Also, the test vectors serve to excite faults downstream of the RAM by propagating values through the RAM needed to excite the downstream faults. The fault effects (if any) that propagate to the circuit primary outputs are compared to a set of reference values to determine if any faults are present.

Claims6

Dependent claims

A method for testing a sequential circuit, including a least one sequential element and at least one embedded RAM linked to said one sequential element via a propagation path that includes at least one node and which extends from one of a set of primary circuit inputs through the RAM to one of a set of primary circuit outputs, comprising the steps of:

generating at least one sequence of test vectors for application to the primary inputs of the circuit to cause a fault at the node to be excited and to cause its effect to propagate through the RAM to said one of said primary circuit outputs when the node is upstream of the RAM and to cause the fault to be excited through the RAM when the node is downstream thereof, and to cause the fault's effect to be propagated to said one of said primary outputs;
applying the sequence of test vectors to the circuit at its primary inputs to cause the circuit to generate response signals at its primary outputs;
and
comparing the responses at the circuit outputs to a set of reference values to determine if any differences exist therebetween.

1 more element

Dependencies are inferred from the claim text.