Test vector generator comprising a decompression control unit and a conditional vector processing unit and method for generating a test vector

A test vector generator for generating a test vector used for testing an integrated circuit having a memory or a logic/memory combination and a plurality of terminals, said terminals including at least:

• a first subset of said terminals at least temporarily operative as address terminals, and
• a second subset of said terminals at least temporarily operative as data terminals, said test vector generator being assigned to a specific terminal of said first subset of terminals of said integrated circuit,
• wherein said test vector generator comprises:
• at least one terminal channel assigned to said terminal or to a specific set of terminals, said terminal channel comprising:
• a sequence controller for generating a first sequence of vectors,
• at least one decompression control unit which is controlled by said first sequence of vectors generated by the sequence controller, generates plural subsequent decompressed signals based on each vector of said first sequence of signals and feeds them to the sequence controller,
• wherein said sequence controller further includes conditional vector processing means for generating a second sequence of vectors by logically combining said first sequence of vectors with the decompressed signals received from said decompression control unit;
• a first counter set up to generate at least the address bit of the assigned terminal of the address of at least one first memory cell, the content of which is held constant during a test cycle;
• and a second counter set up to generate at least the address bit of the assigned terminal of the address of at least one second memory cell, the content of which is varied during a test cycle.

A method for generating a test vector used for testing an electronic device having a memory or a logic/memory combination and a plurality of terminals, said terminals including at least a first subset of terminals at least temporarily operative as address terminals and a second subset of terminals at least temporarily operative as data terminals,

• said method comprising the steps of:
• generating a first sequence of vectors,
• generating plural subsequent decompressed signals based on each vector of said first sequence of signals,
• generating a second sequence of vectors by logically combining said first sequence of vectors with the decompressed signals, and
• applying the second sequence of vectors to said terminals or to said specific set of terminals.