Packet data reciever with sampled data output and background light cancellation
AssigneeAT&T Corp.
InventorsTheo W. M. Mosch, Yusuke Ota, Robert G. Swartz, Richard A. van Wijk
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Abstract
A digital burst-mode packet data receiver receives high-speed burst-mode packet data signals superimposed on a lower frequency data signal. The receiver includes a first detector for detecting the received high-speed burst-mode packet data which is reset during the time period between consecutive bursts of the high-speed packet data signal. A second detector detects the lower frequency data signal during a predetermined portion of the time period between consecutive bursts of the high-speed packet data.
Claims21
A digital burst-mode packet data receiver for simultaneously receiving a high-speed burst-mode packet data signal and a lower frequency data signal, comprising.
- first means for detecting the high-speed burst-mode packet data signal,
- means for receiving a reset signal during a time period between consecutive packet data bursts of the high-speed packet data signal,
- means, responsive to said reset signal, for resetting the first means for detecting to a reference level, and
- second means, responsive to said reset signal, for detecting the lower frequency data signal during a predetermined portion of the time period between consecutive packet data bursts of the high-speed packet data without interference from said high-speed burst-mode packet data signal.
A digital burst-mode packet data receiver for receiving high-speed burst-mode packet data and lower frequency data signals, comprising
- means for detecting the high-speed burst-mode packet data so that said lower frequency data signals do not affect detection of the high-speed burst-mode packet data,
- means for resetting the burst-mode packet data detector to a reference level in response to a first state of a received reset signal occurring between consecutive bursts of the high-speed packet data, and
- means for detecting the lower frequency data signals, in response to both the first state of the received reset signal and a received sample signal, such that said high-speed burst-mode packet data does not affect detection of the lower frequency data signal.
A digital packet data receiver for receiving bursts of digital packet data, comprising
- a DC-coupled differential input amplifier circuit having first input means for receiving said digital packet bursts, second input means for receiving a reference signal, and output means for outputting a data output signal;
- first detector means for detecting and storing a peak amplitude of said data output signal and for generating said reference signal at an output port;
- second detector means for generating a sample data output signal of said data output signal in response to both an inter-packet reset signal and a sampled control input signal;
- and
- selector means, responsive to said reset signal, for
- a) disconnecting said first detector means output port from said second input means of said input amplifier circuit and discharging said peak amplitude signal stored by said first detector means, and
- b) connecting a precision reference voltage as said reference signal to said second input means of said input amplifier circuit.
A digital burst-mode packet data receiver for simultaneously receiving a high-speed burst-mode packet data signal and a lower frequency data signal, comprising:
- first detector means, enabled during a first time period occurring during a received burst of the high-speed packet data signal, for detecting the high-speed burst-mode packet data, and reset to a reference level during a second time period occurring between consecutive bursts of the high-speed packet data signal, and
- second detector means, operable independent of said first detector means and enabled during a predetermined time period, for detecting the lower frequency data signal.
Dependencies are inferred from the claim text.