US 5,499,218 A · Method for driving bit line selecting signals

Abstract

A method for driving bit line selecting signals is disclosed, in which the DRAM cell includes a plurality of memory cell arrays, sense amplifiers, bit lines, bit line equalizer sections, bit line selecting sections, data input/output sections, and bit line selection signal generating sections. According to the present invention, the bit line selecting signals operate in such a manner that: during a bit line selection, a bit line selecting signal for connecting one pair of bit lines among the n pairs of bit lines to the sense amplifier is made to have a voltage level capable of connecting the bit lines to the sense amplifier by the help of the bit line selecting section without a voltage loss; the other bit line selecting signals corresponding to the non-selected remaining bit lines are given a voltage incapable of connecting the bit lines the sense amplifier by the bit line selecting section; thereafter, during the pre-charging for a bit line equalization, the bit line selecting signal corresponding to the bit line which was selected just before is given a voltage capable of connecting the bit lines to the sense amplifier by the help of the bit line selecting section; and the bit line selecting signals which do not correspond to the bit line selected just before are maintained without a voltage shifting.

Claims6

Dependent claims

A method for driving bit line selecting signals in a DRAM having a plurality of memory cell arrays, bit lines connected to a plurality of memory cells included in said memory cell arrays, a bit line equalizer section for pre-charging said bit lines, a sense amplifier section connected to bit line pairs for reading cell data, a bit line selection signal generating section for generating bit line selecting signals, a bit line selecting section for connecting the pairs of said bit lines to said sense amplifier section, and a data input/output section, said method characterized in that:

during a bit line selection, a bit line selecting signal for connecting one pair of said bit lines among the n pairs of said bit lines to the sense amplifier is made to have a voltage (Vpp) level capable of connecting said bit line to said sense amplifier by the help of said bit line selecting section without a voltage loss;
and the other bit line selecting signals corresponding to the non-selected remaining bit lines are made to have a voltage (Vss) incapable of connecting the bit lines to the sense amplifier by said bit line selecting section;
and
thereafter, during the pre-charging for a bit line equalization, the bit line selecting signal corresponding to the bit line which was selected just before is given a voltage (Vcc) capable of connecting the bit line to the sense amplifier by the help of said bit line selecting section;
and the bit line selecting signals which do not correspond to the bit line selected just before are maintained without a voltage shifting.

2 more elements

Dependencies are inferred from the claim text.

Method for driving bit line selecting signals

Life of this patent

Method for driving bit line selecting signals

Life of this patent

Abstract

Claims6