Bias circuit for a memory line decoder driver of nonvolatile memories
AssigneeSGS-Thomson Microelectronics S.A.
InventorsLuigi Pascucci, Carla M. Golla, Marco Maccarrone
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Abstract
A memory line decoding driver is so biased that the P channel pull-up transistor biasing the final inverter conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage alternatively connects the gate terminal of the pull-up transistor to a capacitor, with which the charge is distributed, and to the supply.
Claims23
A bias circuit for a memory line decoder driver of nonvolatile memories, wherein said driver comprises final drive means, and pull-up transistor means connected between a first reference potential line and the input of said final drive means;
- said drive means being designed to switch during transient selection and deselection phases, and to maintain a steady state during static phases interposed between said transient phases;
- said bias circuit comprising generating means for generating a variable bias signal for said pull-up transistor means;
- wherein said generating means includes switching means for switching said bias signal between a first level corresponding to a weak turn-on state of said transistor means at least during said static phases, and a second level corresponding to a high turn-on state of said transistor means during said transient deselection phases.
A method of biasing a memory line decoding driver of nonvolatile memories, said driver comprising final drive means, and pull-up transistor means connected between a first reference potential line and the input of said final drive means;
- said final drive means being designed to switch during transient selection and deselection phases, and to maintain a steady state during static phases interposed between said transient phases;
- said method comprising the step of generating a variable bias signal for said pull-up transistor means;
- characterized by the fact that said generating step comprises the step of switching said bias signal between a first level corresponding to a weak turn-on state of said transistor means at least during said static phases, and a second level corresponding to a high turn-on state of said transistor means during said transient deselection phases.
A bias circuit for a memory line decoder driver of nonvolatile memories, wherein the decoder driver comprises a memory word line driver and a switch having a bias input for selectively coupling a supply electric potential to an input of the word line driver, and wherein the bias circuit comprises:
- a control input coupled to an address phase signal;
- a bias output coupled to the decoder driver switch bias input;
- and
- a switch for alternately coupling a high bias electric potential and a threshold bias electric potential to the bias output in response to the address phase signal, wherein the high bias electric potential is sufficient to bias the decoder driver switch substantially beyond its threshold bias and the threshold bias electric potential is sufficient to bias the decoder driver switch substantially at its threshold bias.
A method of biasing a memory line decoder driver of nonvolatile memories, comprising the steps of:
- receiving an address phase signal;
- providing a switch signal which is a function of the address phase signal;
- alternately outputting a high bias electric potential and a threshold bias electric potential in response to the switch signal, wherein the high bias electric potential is sufficient to bias the decoder driver substantially beyond its threshold bias and the threshold bias electric potential is sufficient to bias the decoder driver substantially at its threshold bias.
A nonvolatile memory system comprising:
- a memory device;
- a memory line decoder driver including a memory word line driver and a switch having a bias input for selectively coupling a supply electric potential to an input of the word line driver;
- and
- a bias circuit including:
- a control input coupled to an address phase signal;
- a bias output coupled to the decoder driver switch bias input;
- and
- a switch for alternately coupling a high bias electric potential and a threshold bias electric potential to the bias output in response to the address phase signal wherein the high bias electric potential is sufficient to bias the decoder driver switch substantially beyond its threshold bias and the threshold bias electric potential is sufficient to bias the decoder driver switch substantially at its threshold bias.
Dependencies are inferred from the claim text.