US 5,499,216 A · Semiconductor memory device selectively operating divided memory blocks

Abstract

A sub row selector is provided in addition to a row selector in a semiconductor memory device selectively operating a plurality of divided memory blocks. A selector of the sub row selector generates a sub row select signal for connecting a bit line pair corresponding to a selected row address and an input/output data line pair in a selected memory block in response to a memory block select signal and a corresponding row select signal. Therefore, only in a selected memory block, a bit line pair corresponding to the selected row address and the input/output data line are connected. As a result, it is possible to selectively operate memory blocks divided in plural with a potential difference between the initial charge potential of each bit line pair and the initial charge potential of each input/output data line pair in a non-selected memory block.

Claims11

Dependent claims

A semiconductor memory device, comprising:

a plurality of memory blocks having a plurality of common row addresses and being operated selectively,
said plurality of memory blocks each including
a plurality of memory cell arrays,
a plurality of bit line pairs provided corresponding to said plurality of memory cell arrays and corresponding to said plurality of common row addresses,
a plurality of switching means provided corresponding to said plurality of bit line pairs, and
an input/output data line pair connected to said plurality of bit line pairs through said plurality of switching means;
first row selecting means for generating a row select signal selecting a common row address;
and
second row selecting means receiving a memory block select signal indicating selected said memory block and said row select signal, and responsive to these signals for turning on said switching means corresponding to the selected row address in the selected memory block.

6 more elements

A semiconductor memory device, comprising:

a plurality of memory blocks having a plurality of common row addresses and being operated selectively,
said plurality of memory blocks each including
a plurality of memory cell arrays,
a plurality of bit line pairs provided corresponding to said plurality of memory cell arrays and corresponding to said plurality of common row addresses,
a plurality of switching means provided corresponding to said plurality of bit line pairs, and
an input/output data line pair connected to said plurality of bit line pairs through said plurality of switching means;
first row selecting means for generating a row select signal for selection one of said common row addresses;
and
a plurality of second row selecting means provided corresponding to said plurality of common row addresses and each receiving a memory block select signal indicating a selected memory block and corresponding said row select signal, for turning on said switching means corresponding to the selected common row address in the selected memory block in response to these signals.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device selectively operating divided memory blocks

Life of this patent

Semiconductor memory device selectively operating divided memory blocks

Life of this patent

Abstract

Claims11