Oscillator circuit generating a clock signal having a temperature dependent cycle and a semiconductor memory device including the same

A semiconductor memory device comprising:

• (a) a memory cell array including a plurality of memory cells requiring a refresh operation,
• (b) an oscillator circuit including
• reference current generation means including
• potential generation means for generating an output potential varying in response to an operating temperature, and
• voltage-current conversion means for generating a reference current varying in response to said output potential, and
• oscillator means including an odd number of a plurality of inverter means connected in a ring manner, and means responsive to said reference current for supplying a charge current and/or a discharge current from an output node of at least one of said plurality of inverter means to an input node of the inverter means having an input node connected to said output node, said oscillator means providing a clock signal from an output node of the inverter means of the last stage, and
• (c) refresh means responsive to said clock signal for carrying a refresh operation for said plurality of memory cells.

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells requiring a refresh operation,
• an oscillator circuit including
• reference current generation means having a reference transistor in which a reference current varying in response to an operating temperature flows, and
• oscillator means including an odd number of a plurality of inverter means connected in ring manner, wherein each of said plurality of inverter means comprises an input node, an output node, a first transistor connected between a first power supply potential node and said output node and having a control electrode connected to said input node, and a second transistor connected between said output node and a second power supply potential node, and having a control electrode connected to said input node, wherein at least one of said plurality of inverter means further includes a control transistor forming a current mirror circuit with said reference transistor, and connected between said output node and said second power supply potential node, in series with said second transistor, said oscillator means providing a clock signal from the output node of an inverter means of the last stage, and
• refresh means responsive to said clock signal for carrying out a refresh operation for said plurality of memory cells.

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells requiring a refresh operation,
• an oscillator circuit including
• reference current generation means having a reference transistor in which a reference current varying in response to an operating temperature flows, and
• oscillator means including an odd number of a plurality of inverter means connected in a ring manner, wherein each of said plurality of inverter means comprises an input node, an output node, a first transistor connected between a first power supply potential node and said output node, and having a control electrode connected to said input node, and a second transistor connected between said output node and a second power supply potential node, and having a control electrode connected to said input node, wherein at least one of said plurality of inverter means further includes a control transistor forming a current mirror circuit with said reference transistor, connected between said first power supply potential node and said output node, in series with said first transistor, said oscillator means providing a clock signal from the output node of an inverter means of the last stage, and
• refresh means responsive to said clock signal for carrying out a refresh operation for said plurality of memory cells.

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells requiring a refresh operation,
• an oscillator circuit including
• reference current generation means, wherein said reference current generation means includes a reference P channel transistor in which a reference current flows varying in response to an operating temperature, and a reference N channel transistor in which a reference current flows varying in response to an operating temperature, and
• oscillator means including an odd number of a plurality of inverter means connected in a ring manner, each of said plurality of inverter means including an input node, an output node, a P channel transistor, connected between a first power supply potential node and said output node, and having a control electrode connected to said input node, and an N channel transistor, connected between said output node and a second power supply potential node, having a control electrode connected to said input node, wherein at least one of said plurality of inverter means further includes a control P channel transistor forming a current mirror circuit with said reference P channel transistor, connected between said first power supply potential node and said output node, in series with said P channel transistor, and a control N channel transistor forming a current mirror circuit with said reference N channel transistor, connected between said output node and said second power supply potential node, in series with said N channel transistor, said oscillator means providing a clock signal from an output node of the inverter means of the last stage,
• refresh means responsive to said clock signal for carrying out a refresh operation for said plurality of memory cells.

A semiconductor memory device, comprising:

• a memory cell array including a plurality of memory cells requiring a refresh operation;
• an oscillator circuit including
• reference current generation means, wherein said reference current generation means includes a reference P channel transistor in which a reference current flows varying in response to an operating temperature, and a reference N channel transistor in which a reference current flows varying in response to an operating temperature, and
• oscillator means including an odd number of a plurality of inverter means connected in a ring manner, each of said plurality of inverter means including an input node, an output node, a P channel transistor, connected between a first power supply potential node and said output node, and having a control electrode connected to said input node, and an N channel transistor, connected between said output node and a second power supply potential node, having a control electrode connected to said input node, wherein at least one of said plurality of inverter means further includes a control P channel transistor forming a current mirror circuit with said reference P channel transistor, connected between said first power supply potential node and said output node, in series with said P channel transistor, and a control N channel transistor forming a current mirror circuit with said reference N channel transistor, connected between said output node and said second power supply potential node, in series with said N channel transistor, said oscillator means providing a clock signal from an output node of the inverter means of the last stage, and
• a refresh means responsive to said clock signal for carrying out a refresh operation for said plurality of memory cells;
• wherein said reference current generation means comprises
• potential generation means for generating an output potential varying in response to an operating temperature, and
• voltage-current conversion means for generating a current varying in response to said output potential, and
• wherein said reference current flows in said reference P and N channel transistors in response to said current generated by said voltage-current conversion means.