US 5,499,209 A · Integrated semiconductor memory with internal voltage booster of lesser dependency on power supply voltage

Abstract

A word-line drive voltage generation circuit for use in a dynamic random-access memory is disclosed which is connected to a word line via a row decoder including MOS transistors. The circuit includes a charge-bootstrap capacitor having insulated electrodes, one of which is connected to a first reference voltage generator via a switching MOS transistor, and the other of which is connected via a MOS transistor to a second reference voltage generator. These voltage generators provide the capacitor with the constant d.c. voltage that are essentially insensitive to variation in the power supply voltage for the memory. The resultant word-line drive voltage may thus be free from variation in the power supply voltage during the operation modes of the memory. This enables the word-line voltage to be high enough to allow successful "H" level writing at a selected memory cell without creation of any unwantedly increased dielectric breakdown therein, in the entire allowable range of the power supply voltage.

Claims9

Dependent claims

A random-access memory comprising:

an array of rows and columns of memory cells, each of which has a data storage capacitor and a data transfer transistor;
bit lines associated with said memory cells at current carrying electrodes of said transistors;
word lines associated with said memory cells at control gates of said transistors;
and
a driver circuit coupled with said word lines, for receiving a power supply voltage of said memory, for generating a specific potential-increased voltage of a preselected potential level that is essentially insensitive to variation in the power supply voltage during an operation of said memory, and for supplying a selected word line with the specific voltage as a drive voltage therefor, said driver circuit including at least one capacitor having a first insulated electrode and a second insulated electrode, and a circuit for supplying a regulated voltage, which is substantially independent of variation in the power supply voltage, to at least one of said first insulated electrode and second insulated electrode.

2 more elements

A random access memory comprising:

an array of rows and columns of memory cells, each of which has a data storage capacitor and a data transfer transistor;
bit lines associated with said memory cells at current carrying electrodes of said transistor;
word lines associated with said memory cells at control gates of said transistors;
and a drive circuit coupled with said word lines, for receiving a power supply voltage of said memory, for generating a specific potential-increased voltage of a preselected potential level that is essentially insensitive to variation in the power supply voltage during an operation of said memory, and for supplying a selected word line with the specific voltage as a drive voltage therefor, wherein said driver circuit comprises:
a charge-up capacitor having a first and a second insulated electrodes;
a first circuit connected to the first electrode, for supplying it with a first regulated d.c. voltage that is substantially independent of variation in the power supply voltage and holds a fixed potential;
and
a second circuit connected to the second electrode, for supplying it with a second regulated d.c. voltage that is substantially independent of variation in the power supply voltage and holds a fixed potential.

5 more elements

Dependencies are inferred from the claim text.

Integrated semiconductor memory with internal voltage booster of lesser dependency on power supply voltage

Life of this patent

Integrated semiconductor memory with internal voltage booster of lesser dependency on power supply voltage

Life of this patent

Abstract

Claims9