Integrated circuit memory device

#The present invention relates to the field of integrated circuit memory devices, and in particular, to methods and apparatus for accessing data therefrom.

#Integrated circuit read only memory (ROM) devices are devices that contain a permanent set of information written into the memory. Under ordinary operation, the content of the memory remains unchanged. Such devices are useful in a variety of applications such as in microprocessor applications where permanent microprocessor instructions are stored within a ROM device.

#At present, ROM devices ordinarily comprise an array of memory cells, where each memory cell contains information comprising one digital bit. The ROM array consists of several y-select lines, or columns, and several x-select lines, or rows. Each memory cell is connected between one of the y-select lines and one of the x-select lines, giving each cell a unique x,y address. In order to read the information therein, one of the y-select lines and one of the x-select lines are enabled or switched on, while the remainder remain switched off. When the enable lines are switched off, they are effectively open circuited. In this manner, only one memory cell is connected to an active circuit at a time.

#FIG. 1 shows a memory circuit according to the present invention comprising one row of five memory cells wherein each cell comprises a resistor;

#FIGS. 2(a)-2(g) show signal waveforms at various points within the memory circuit device illustrated in FIG. 1 during normal operation;

#FIG. 3 shows a ramp step signal source which may be employed in the memory circuit device illustrated in FIG. 1;

#FIG. 1 shows a memory circuit 100 that operates according to the present invention. The memory circuit comprises a read signal source 110, a row of five memory cells or resistors 131 through 135 and a readout circuit 150. It will be understood that the memory circuit 100 is given by way of example only, and the use of an example consisting of five memory cells is chosen to illustrate the operation of the invention. The methods and principles of the circuit 100 may readily be extended to a circuit consisting of a substantially greater number of memory cells by those of ordinary skill in the art, and it is well understood that a typical memory device may include many thousands of bits. An example of a larger scale memory device operating in accordance with the principles of the present invention is discussed below in connection with FIG. 10.

#The elements of the memory circuit 100 are preferably integrated onto a single semiconductor substrate. The read signal source 110 includes five outputs 121 through 125 and may suitably comprise the circuit described below in connection with FIG. 3. Each of the outputs 121 through 125 is connected to the first terminal of one of the five memory resistors 131 through 135, such that the first output 121 is connected to the first resistor 131, the second output 122 is connected to the second resistor 132, and so forth. Each resistor has two terminals, such as terminals 131a and 131b in the resistor 131. The resistors 131 through 135 may be implemented as any resistors suitable for use in an integrated circuit, such as thin-film deposited resistors or ion-implanted resistors. The resistive values typically range from 100 k.OMEGA. to 20 M.OMEGA., the particular resistance value being representative of the information or data value that is to be stored in the cell. For example, a 100 k.OMEGA. resistor represents one data value, a 400 k.OMEGA. resistor represents another, and so forth.

#Each of the second terminals of the memory resistors 131 through 135 are commonly connected to a sum line 140. The sum line 140 is connected to the readout circuit 150 which includes to both a load resistance 155 and a read out circuit comprising a buffer 151 having an input and an output, a capacitor 162 and a resistor 164. The sum line 140 is connected to one input of the buffer 151. The buffer 151 may suitably be a high input impedance unity gain buffer. The load resistance 155 is preferably much larger in resistance value than the memory resistors 131 through 135. In fact, the load resistance 155 may suitably comprise the internal input impedance of the buffer 151.