Memory cache with interlaced data and method of operation

A memory cache outputting A contiguous elements from a memory space responsive to an address, the memory cache comprising:

• a plurality of cache lines comprising A sections, the plurality of cache lines outputting one of the plurality of cache lines responsive to a first subset of the address, each one of the plurality of cache lines storing E contiguous elements from the memory space, each one of the E contiguous elements comprising C bits, each one of the A sections comprising C subsections of either B or (B-1) adjacent bits, an Ith subsection in a Kth section storing an Ith bit of a (0*A+K)th, a(1*A+K)th, a(2*A+K)th, a (. . .)th, and a ((B-1-P)*A+K)th one of the E contiguous elements, a "set of interlaced elements," where A, B, C, I, K, E, and P are integers, where B is a ratio of (E/A) rounded to a next higher integer, where I is an index ranging from zero to C-1, where K is an index ranging from zero to A-1, where P equals zero if a remainder of (E/A) is zero or if K is less than a non-zero remainder of (E/A), and where P equals one if K is greater than or equal to the non-zero remainder of (E/A);
• a first set of C-bit switching means, each switching means of the first set of C-bit switching means receiving the interlaced elements from a differing one of the A sections, each switching means of the first set of C-bit switching means outputting an element responsive to a second subset of the address;
• and
• a second set of C-bit switching means, each switching means of the second set of C-bit switching means receiving the element from each one of the first set of C-bit switching means, each switching means of the second set of C-bit switching means outputting a differing one of A elements responsive to a third subset of the address, an order of the A elements output by the second set of C-bit switching means equivalent to an order of the A elements in the memory space.

A method of operating a memory cache comprising the steps of:

• receiving an address in a plurality of cache lines, the address indexing an initial memory element in a memory space, the initial memory element being a first one of a series of A contiguous memory elements, each one of the plurality of cache lines comprising A sections, each one of the plurality of cache lines storing E contiguous elements from the memory space, each one of the E contiguous elements comprising C bits, each one of the A sections comprising C subsections of either B or (B-1) adjacent bits, an Ith subsection in a Kth section storing an Ith bit of a (0*A+K)th, a (1*A+K)th, a (2*A+K)th, a (. . .)th, and a ((B-1-P)*A+K)th one of the E contiguous elements, where A, B, C, I, K, E, and P are integers, where B is a ratio of (E/A) rounded to a next higher integer, where I is an index ranging from zero to C-1, where K is an index ranging from zero to A-1, where P equals zero if a remainder of (E/A) is zero or if K is less than a non-zero remainder of (E/A), and where P equals one if K is greater than or equal to the non-zero remainder of (E/A);
• first selecting one of the plurality of cache lines responsive to the address;
• second selecting A memory elements of the set of interlaced elements;
• and
• reordering the A memory elements such that an order of the A memory elements is equivalent to the series of A contiguous memory elements.