Logic elements for interlaced carry/borrow systems having a uniform layout

The logic array of claim 8 said logic array being used to provide an in-phase signal pair (N-1) generate and (N-1) integrate for the less significant N-1bits of said first (X) and second (Y) N.sub.-- bit-vector signals each defining a binary number, where bit N represents a sign signal, said in-phase signal pair being utilized to define the mathematical inequalities (X>Y), (X.gtoreq.Y), (X<Y) and (X.ltoreq.Y) as logical conditions, said logic array further comprising:

• a logic element according to claim 30 wherein said A2-B2input termination pair thereof is respectively connected to said Aout.sub.-- i and Bout.sub.-- i output pairs at bit-position (2 exp (L)-1) and wherein said A1-B1 input termination pair thereof is respectively connected to said Aout.sub.-- i and Bout.sub.-- i output pairs at bit-position i=(2exp (L-1)),
• and wherein said Ao-Bo output termination pair thereof provide said N-1 generate (G(N-1, 1 ) ) and N-1 integrate (I(N-1, 1)) signals. and wherein said Ain.sub.-- i and Bin.sub.-- i input pair for i=N provides G(N) and P(N) signals,
• said G(N), P(N), G(N-1, 1) and I(N-1, 1) signals and their respective inverted signals being used for determining the presence of said logical conditions according to the following logical statements:
• (1) (X>Y) IF G(N)+P(N).multidot.G(N-1, 1) IS TRUE;
• (2) (X>Y) IF G(N)+P(N).multidot.I(N-1, 1) IS TRUE;
• (3) (X<Y) IF P(N)+G(N) .multidot.I (N-1, 1) IS TRUE;
• and
• (4) (X.ltoreq.Y) IF P(N)+G(N).multidot.G(N-1, 1) IS TRUE.

A logic element defined as a Binary Noninverting Cell (BN-cell) comprising:

• two pairs of first and second inverting-type logic gates, each pair defining a combined gate;
• a pair of first and second output terminations Ao-Bo;
• and
• first and second input termination pairs, each pair having first and second input terminations A1-B1 and A2-B2,
• said first inverting-type logic gate of said first combined gate providing its output to an input of said second inverting-type logic gate of said first combined gate,
• said first inverting-type logic gate of said second combined gate providing its output to an input of said second inverting-type logic gate of said second combined gate.
• said first input termination (A1) of said first input termination pair being connected to an input of said first inverting-type logic gate of said first combined gate,
• said second input termination (B1) of said first input termination pair being connected to an input of said first inverting-type logic gate of said second combined gate,
• said first input termination (A2) of said second input termination pair being connected to an input of said first inverting-type logic gate of said first combined gate, and to an input of said second inverting-type logic gate of said second combined gate,
• said second input termination (B2) of said second input termination pair being connected to an input of said first inverting-type logic gate of said second combined gate, and to an input of said second inverting-type logic gate of said first combined gate,
• said second inverting-type logic gate of said first combined gate having its output connected to said first output termination (Ao),
• said second inverting-type logic gate of said second combined gate having its output connected to said second output termination (Bo),
• wherein said input termination pairs A1-B1, A2-B2 are respectively provided with input singnal pairs Sa1-Sb1, Sa2-Sb2, said input signal pairs having the logical IMPLY relationship:
• Sai+Sbi=1,
• and wherein said first and second output termination pair Ao-Bo providing, respectively, a binary output signal pair Sao and Sbo,
• and wherein said logic element is characterized in that said first and second binary output signals Sao and Sbo are related by the logical IMPLY relationship,
• Sao+Sbo =1.

A logic element having complementary output signals being defined as a Complementary Output (CO) cell, said CO cell comprising:

• a pair of first and second logical circuits, said first logical circuit providing binary complemented output signals Sao.sub.-- 1 and Sao.sub.-- 0, and said second logical circuit providing binary complemented output signals Sbo.sub.-- 1 and Sbo.sub.-- 0,
• each of said logical circuits having at least first, second and third OR-NOR gates and at least first and second input termination pairs (Di;Ei) of first (Di) and second (Ei) inputs, wherein inputs D1, E1, D2 and E2 of said second logical circuit correspond to input D1, E1 D2 and E2 of said first logical circuit, having repective, binary complemented input signals, wherein
• said first input D1 of said first input termination pair in each of said logical circuits being connected to an input of both said first and second OR-NOR gates,
• said second input E1 of said first input termination pair in each of said logical circuits being connected to another input of both said first and second OR-NOR gates,
• said first input D2 of said second input termination pair in each of said logical circuits being connected to an input of both said first and third OR-NOR gates,
• said second input E2 of said second input termination pair in each of said logical circuits being connected to an input of both said second and third OR-NOR gates,
• a Nor output of each of said first, second and third OR-NOR gates of said first logical circuit being provided as a separate input to an OR gate having as its output said binary output signal (Sao.sub.-- 1)
• an Or output of each of said first, second and third OR-NOR gates of said first logical circuit being commonly connected to form a wired-AND gate, having as its output said binary output signal (Sao.sub.-- 0),
• a Nor output of each of said first, second and third OR-NOR gates of said second logical circuit being provided as a separate input to an OR gate having as its output said binary output signal (Sbo.sub.-- 1),
• an Or output of each of said first, second and third OR-NOR gates of said second logical circult being commonly connected to form a wired-AND gate, having as its output said binary output signal (Sbo.sub.-- 0),
• wherein said first binary output signal Sao.sub.-- 1 of said first logical circuit and said first binary output signal Sbo.sub.-- 1 of said second logical circuit are related by the IMPLY relationship:
• Sao.sub.-- 1+Sbo.sub.-- 1=1, where Sbo.sub.-- 1 Sao.sub.-- 1, and
• wherein said first binary output signal Sao.sub.-- 0 of said first logical circuit and said first binary output signal Sbo.sub.-- 0 of said second logical circuit are related by the IMPLY relationship:
• Sao.sub.-- 0+Sbo.sub.-- 0=1, where Sbo.sub.-- 0 Sao--0.