Multi-level logic optimization in programmable logic devices

A computerized electronic design system comprising:

• a data storage device, said data storage device having stored therein details of a plurality of programmable electronic devices, each of said devices having one or more registers;
• data input means for inputting data related to a logic circuit into said data storage device;
• and
• computer means for designing said logic circuits for implementation in said one or more programmable electronic devices, said computer means comprising:
• register synthesis means for generating a first register design using at least a first type of register and a second register design using at least a second type of register;
• and
• register selection means for selecting one of said first and second register designs.

A computerized electronic design system comprising:

• a data storage device, said data storage device having stored therein details of a plurality of programmable electronic devices;
• data input means for inputting data related to a logic circuit into said data storage device, said logic circuit having at least one node;
• and
• computer means for designing one or more representations of logic circuits for implementation in one or more of said programmable electronic devices, wherein a first circuit representation relates to the ON state of said node and a second circuit representation relates to the OFF state of said node, said computer means comprising:
• means for determining DONT CARE information from said first circuit representation and said second circuit representation;
• final reducing means for reducing said circuit representations after they have been designed;
• and
• DONT CARE information retaining means for retaining all of said DONT CARE information until said final reducing means reduces said one or more circuit representations;
• and
• implementing means for selecting one or more of said circuit representations and implementing it into a programmable electronic device.

A computerized design system for designing a logic circuit to be implemented in a programmable logic device having a limited logic capability, said system comprising:

• a data storage device;
• data input means for inputting a hardware description of said logic circuit into said data storage device;
• a compiler communicating with said data storage device for determining a plurality of physical nodes from said hardware description and for inserting a plurality of virtual nodes into said hardware description, said compiler also generating one or more equations representative of said logic circuit from said hardware description, said equations including one or more nodal equations representative of said virtual and physical nodes of said logic circuit;
• node minimizing means for minimizing the number of said nodal equations without exceeding the logic capabilities of said programmable logic device;
• and
• implementing means for translating said equations into one or more implementations of said logic circuit in said programmable logic device.

A computerized design system for designing a logic circuit to be implemented in one or more programmable logic devices, said system comprising:

• a data storage device;
• data input means for inputting data to be used in the design of said logic circuit into said data storage device, said data including a maximum symbols parameter;
• compiler means communicating with said data storage device for generating one or more equations representative of said logic circuit, said equations including one or more nodal equations representing nodes of said logic circuit, wherein said equations comprise logical combinations of symbols, each symbol representing one or more components of said programmable logic devices selected from the group comprising:
• inputs to said programmable logic devices, outputs to said programmable logic devices, and nodes of said programmable logic devices;
• node minimizing means for minimizing the number of said nodal equations without causing the number of unique symbols in any one of said equations to exceed said maximum symbols parameter;
• and
• implementing means for translating said minimized number of nodal equations into one or more implementations of said logic circuit in said one or more programmable logic devices.

A computerized design system for designing a logic circuit to be implemented in one or more programmable electronic devices, said system comprising:

• a data storage device;
• data input means for inputting data to be used in the design of said logic circuit into said data storage device;
• compiler means communicating with said data storage device for defining a plurality of nodes within said logic circuit and generating one or more equations representative of said logic circuit, said equations including both an ON representation and an OFF representation for each of said nodes;
• equation minimizing means for minimizing the number of said equations while retaining both the ON and OFF representations for each equation throughout the minimization process thereby retaining all DONT CARE information for said logic circuit;
• and
• implementing means for translating said equations into one or more implementations of said logic circuit in said one or more programmable electronic devices.

A computerized design system for designing a logic circuit to be implemented in one or more programmable logic devices;

• said system comprising:
• a data storage device;
• data input means for inputting data to be used in the design of said logic circuit into said data storage device, said data including a maximum product terms parameter;
• compiler means communicating with said data storage means for determining a plurality of nodes in said logic circuit and for generating one or more sum-of-products equations each having a number of product terms representative of said logic circuit said sum-of-products equations including a number of nodal equations representing nodes of said logic circuit in terms of symbols, said symbols representing one or more components of said programmable logic devices selected from the group comprising:
• inputs to said programmable logic devices, outputs to said programmable logic devices, and nodes of said programmable logic devices;
• node minimizing means for minimizing the number of nodal equations without causing the number of product terms in any one of said equations to exceed said maximum product terms parameter;
• and
• implementing means for translating said equations into one or more implementations of said logic circuit in said one or more programmable logic devices.

A computerized design system for designing a logic circuit to be implemented in one or more programmable logic devices;

• said system comprising:
• a data storage device;
• data input means for inputting data to be used in the design of said logic circuit into said data storage device, said data including a maximum product terms parameter and a binary polarity control parameter;
• compiler means communicating with said data storage device for generating one or more sum-of-products equations, representative of said logic circuit, said sum-of-products equations including both an ON representation including a number of ON-product terms and an OFF representation including a number of OFF-product terms for one or more nodal equations representing nodes of said logic circuit in terms of symbols, said symbols representing one or more components of said programmable logic devices selected from the group comprising:
• inputs to said programmable logic devices, outputs to said programmable logic devices, and nodes of said programmable logic devices;
• node minimizing means for minimizing the number of said nodal equations, said node minimizing means comprising node collapsing means for collapsing a selected nodal equation into the other nodal equations if said polarity control parameter is true and either the number of ON product terms or the number of OFF product terms is less than or equal to said maximum product terms parameter;
• and
• implementing means for translating said equations into one or more implementations of said logic circuit in said one or more programmable logic devices.

A method of designing a logic circuit to be implemented in one or more programmable logic devices, said method comprising the steps of:

• inputting data in a first hardware description format to be used in the design of said logic circuit into a data storage device, said data including a maximum symbols parameter;
• compiling said input data to generate a number of nodal equations representative of nodes of said logic circuit in terms of symbols, said symbols representing one or more components of said programmable logic devices selected from the group comprising:
• inputs to said programmable logic devices, outputs to said programmable logic devices, and nodes of said programmable logic devices;
• minimizing the number of said nodal equations without causing the number of unique symbols in any one of said equations to exceed said maximum signals parameter;
• and
• translating said equations into one or more implementations of said logic circuit in said one or more programmable logic devices.

A method of designing a logic circuit to be implemented in a programmable logic device having a limited logic capability, said method comprising:

• inputting data to be used in the design of said logic circuit into a data storage device;
• generating one or more equations representative of said logic circuit, said equations including one or more nodal equations representative of nodes of said logic circuit;
• minimizing the number of said nodal equations without exceeding the logic capabilities of said programmable logic device;
• and
• translating said equations into one or more implementations of said logic circuit in said programmable logic device.

A method of computerized electronic design comprising the steps of:

• providing a data storage device having stored therein details of a plurality of programmable electronic devices;
• inputting data related to a logic circuit into said data storage device;
• generating a first circuit representation for an ON state of a circuit element and generating a second circuit representation for an OFF state of said circuit element;
• determining DONT CARE information from said first circuit representation and said second circuit representation;
• using said DONT CARE information while reducing said circuit representations;
• and
• selecting one or more of said circuit representations and implementing it into a programmable electronic device.

A method of computerized electronic logic circuit design comprising the steps of:

• providing a data storage device have details of a plurality of programmable electronic devices stored therein, each of said devices having one or more registers;
• inputting data related to a logic circuit into said data storage device, said data including register information;
• designing on a computer one or more logic circuits for implementation in one or more of said programmable electronic devices;
• generating a logic circuit design for every type of register available when said input data specifies a register in said logic circuit;
• and
• selecting and implementing of one of said generated circuit designs.