Protection circuit
AssigneeNEC Corporation
InventorAkira Tamakoshi
Life of this patent
Estimating the term…
Abstract
Independently of a punch-through MOS transistor Q.sub.3 used as an I/O protection element in which the drain is connected to an input node or output node and the source is connected to a GND or Vcc, an element for-setting the gate of punch-through MOS transistor Q.sub.3 to the GND potential is provided so that its operating speed may be slower than the punch-through speed of the punch-through MOS transistor Q.sub.3. In consequence, a high surge applied from I/O terminal can be punched through before the gate insulating film of the punch-through transistor Q.sub.3 undergoes a high electric field, to thereby protect the gate insulating film.
Claims3
A protection circuit, comprising:
- an output line having an output pad at an output terminal thereof;
- a first output transistor for setting said output line to a potential of a power supply Vcc according to a first signal supplied from an internal circuit, said first output transistor being connected to the power supply Vcc;
- a second output transistor for setting said output line to ground level according to a second signal supplied from the internal circuit, said second output transistor being connected to ground level;
- a first punch-through MOS transistor having a first punch through speed and a drain connected to said output line and a source connected to ground level;
- a second punch-through MOS transistor having a second punch through speed and a drain connected to said output line and a source connected to the power supply Vcc;
- and
- a grounding MOS transistor for setting both a gate of said first punch-through MOS transistor and a gate of said second punch-through MOS transistor to ground level, said grounding MOS transistor having a drain connected to both said gate of said first punch-through MOS transistor and said gate of said second punch-through MOS transistor, a source of said grounding MOS transistor being connected to ground level, and a gate of said grounding MOS transistor being connected to the power supply Vcc, said grounding MOS transistor having an operating speed slower than said first punch-through speed of said first punch-through MOS transistor and slower than said second punch-through speed of said second punch-through MOS transistor.
Dependencies are inferred from the claim text.