DMA controller using a predetermined number of transfers per request

A data transfer controller coupled through a bus to a central processing unit, a memory and a peripheral unit and transferring data from said memory to said peripheral unit through said bus in place of said central processing unit in response to a transfer request signal generated from said peripheral unit, said controller comprising:

• first register means for storing address information for accessing an area of said memory, said area storing a plurality of data units to be transferred,
• bus control means responsive to each of said transfer request signals from said peripheral unit for requesting a bus control right for controlling said bus from said central processing unit,
• second register means for storing a first number indicative of an amount of said data units stored in said area of said memory, one of said data units stored in said area of said memory being transferred to said peripheral unit by performing a bus cycle once,
• third register means for storing a second number of data transfers to be successively performed each time said peripheral unit generates said data transfer request signal, said second number stored in said third register means being smaller than said first number stored in said second register means,
• data transfer means, coupled to said first and second register means and said bus control means, for successively performing a plurality of data transfers each time said data peripheral unit generates said transfer request signal to thereby successively transfer a plurality of the data in said memory to said peripheral unit during a number of data transfers designated by said second number in said third register means,
• detector means for returning said bus control right to said central processing unit after each of the data transfers of said plurality of data transfers represented by said number in said third register means is performed by said data transfer means,
• signaling means coupled to said second register means and said data transfer means for informing said central processing unit of the completion of a data transfer when the data transfer performed by said data transfer means reaches said second number stored in said third register means.

A direct memory access (DMA) data transfer controller for transferring data directly between a memory and a peripheral unit, said controller comprising:

• a DMA address generating circuit including a first register for storing address information for accessing an area of said memory storing data to be transferred,
• a DMA request controller and access arbitration circuit, responsive to each transfer request from said peripheral unit, for requesting a bus control right from a central processing unit (CPU),
• a terminal count control circuit including second register means for storing a number of cycles to be performed each time said transfer request is generated from said peripheral unit, one of said data stored in said area of said memory being transferred to said peripheral unit by performing a bus cycle once,
• a DMA count control circuit including third and fourth registers each storing a different number of bus cycles to be performed in response to a transfer request;
• a selector connected to said second and third registers for selecting information stored in one of said third and fourth registers, depending on a type of transfer request from said peripheral unit;
• said central processing unit generating a bus cycle signal coupled to said DMA address generating circuit, said DMA terminal count control circuit and said DMA request controller and access arbitration circuit performing a data transfer between said memory and said peripheral unit a number of times corresponding to said number of cycles stored in said second register;
• a detector for returning said bus control right to said central processing unit after each of said data transfers of said plurality of data transfers designated by said number of cycles stored in said second register, is performed;
• and
• a DMA response controller coupled to said terminal count control circuit for informing said central processing unit of the completion of a data transfer when the bus cycle performed reaches a number represented by the number stored in said second register.

An information processing device, comprising:

• a bus;
• a memory coupled to said bus;
• a destination unit coupled to said bus and generating a transfer request signal;
• a central processing unit coupled to said bus and receiving a bus control request signal, a bus control returning signal and a transfer completion signal;
• and
• a data transfer controller coupled to said bus, said data transfer controller for receiving said transfer request signal and generating said bus control request signal, said bus control returning signal and said transfer completion signal;
• wherein said data transfer controller comprises:
• a first register for storing address information for accessing an area of said memory, said area storing a plurality of data units to be transferred;
• a second register for storing a first number indicative of a total number of data transfers;
• a third register for storing a second number of data transfer to be successively performed each time said destination unit generates said data transfer request signal;
• a bus control circuit for sending said bus control requesting signal responsive to each of said transfer request signals from said destination unit;
• a data transfer circuit coupled to said first and second registers and said bus control circuit for successively performing a plurality of data transfers each time said data destination unit generates said transfer request signal to thereby successively transfer a plurality of the data units in said memory to said destination unit during a number of transfers designated by said second number stored in said third register;
• a detecting circuit for sending said bus control returning signal after each of the data transfers of the plurality of data transfers designated by said second number stored in said third register, is performed by said data transfer circuit;
• and
• a signaling circuit coupled to said second register and said data transfer circuit for sending said transfer completion signal when the data transfers performed by said data transfer circuit reaches said second number stored in said second register,
• wherein said central processing unit sets contents of said data transfer controller when said destination unit sends said transfer request signal after said data transfer controller generates said transfer completion signal.

An information processing device, comprising:

• a bus;
• a memory coupled to said bus;
• a destination unit coupled to said bus and generating a transfer request signal;
• a central processing unit coupled to said bus and receiving a bus control request signal, a bus control returning signal and a transfer completion signal;
• and
• a data transfer controller coupled to said bus, said data transfer controller receiving said transfer request signal and generating said bus control request signal, said bus control returning signal and said transfer completion signal,
• wherein said data transfer controller comprises:
• a first register for storing address information for accessing an area of said memory, said area for storing a plurality of data units to be transferred;
• a second register for storing a first number;
• a third register for storing a second number of data transfer to be successively performed each time said destination unit generates said data transfer request signal;
• a bus control circuit for sending said bus control requesting signal responsive to each of said transfer request signal from said destination unit;
• a data transfer circuit, coupled to said first and second registers and said bus control circuit, for successively performing a plurality of data transfers each time said data destination unit generates said transfer request signal, to thereby successively transfer a plurality of the data in said memory to said destination unit during a number of data transfers designated by said second number in said third register;
• a detecting circuit for sending said bus control returning signal after each of the data transfers of the plurality of data transfers designated by said number in said third register, is performed by said data transfer circuit;
• a signaling circuit, coupled to said second register and said dam transfer circuit, for sending said transfer completion signal when a number of said transfer request signals generated by said destination unit reaches said first number stored in said second register,
• wherein said central processing unit sets contents of said data transfer controller when said destination unit sends said transfer request signal after said data transfer controller generates said transfer completion signal.