Superscalar risc instruction scheduling

A register renaming system for a set of RISC instructions in an instruction window, adapted for use in a computer comprising an instruction execution unit which executes the instructions to generate execution results, the system comprising:

• data dependence check means for determining data dependencies between the instructions in the instruction window;
• means for assigning instruction tags to the execution results of each instruction in the instruction window based on the location of each instruction in the instruction window;
• and
• storage means including,
• register file locations for storing retired instruction results, and
• temporary storage locations for temporarily storing the execution results according to said instruction tags prior to completion of all the instructions in the set of RISC instructions, wherein said instruction tags represent addresses within said temporary storage locations.

A system for register renaming in a computer system capable of out-of-order instruction execution, comprising:

• an instruction window for storing a plurality of instructions;
• a temporary buffer comprising a plurality of storage locations for storing instruction data, wherein said instruction data for an instruction are stored at one of said plurality of storage locations, said one of a plurality of storage locations being determined by a location of said instruction in said instruction window;
• dependency check means for identifying dependencies among said plurality of instructions;
• tag assignment means for receiving data dependency results from said dependency check means and for outputting a tag in place of a register address for an operand of a first instruction if said first instruction is dependent on a previous one of said plurality of instructions in said instruction window for said operand;
• wherein said tag represents an address of said operand in one of said plurality of storage locations.