US 5,497,497 AGranted

Method and apparatus for resetting multiple processors using a common ROM

AssigneeCompaq Computer Corporation

InventorsDavid A. Miller, Kenneth A. Jansen, Montgomery C. McGraw, Darren J. Cepulis

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Abstract

Two design variations which allow multiple processors to start up using a single ROM. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.

Claims21

Dependent claims

A method for powering up multiple processors in a computer system that includes a primary processor which commences operation on power-up of said computer system, a secondary processor which enters a hold state on power-up of said computer system, the primary processor and the secondary processor being powered up together, common elements used by both said primary processor and secondary processor, means coupled to said primary processor and said secondary processor for allowing said hold state of said secondary processor to be terminated, means for storing a redirection vector, and means for storing a start-up program which includes as one step determining whether said redirection vector is to be utilized, said start-up program including initialization code used to initialize said secondary processor, the method comprising:

said primary processor commencing said start-up program and not utilizing said stored redirection vector, said start-up program including steps for initializing said primary processor and steps for initializing said common elements of the computer system;
said primary processor completing appropriate initialization of said computer system;
said primary processor placing a redirection vector pointing to said secondary processor initialization code in said redirection vector storing means;
said primary processor activating said secondary processor;
said secondary processor commencing said start-up program and utilizing said stored redirection vector to begin execution of said secondary processor initiation code after said primary processor places said redirection vector, wherein said secondary processor initialization code is only a subset of operations comprised in said start-up program and does not include said steps for initializing said common elements of said computer system;
and
said secondary processor executing said secondary processor initialization code.

4 more elements

A computer system having multiple processors configured in a multiprocessor environment sharing memory and input/output space, said computer system comprising:

a primary processor which commences operation on power-up of said computer system;
a secondary processor which enters a hold state on power-up of said computer system, said secondary processor powering-up at the same time as said primary processor;
means coupled to said primary processor and said secondary processor for allowing said hold state of said secondary processor to be terminated;
means coupled to said primary processor and said secondary processor for storing a start-up program which determines whether a redirection vector is to be utilized, which is begun by both said primary processor and said secondary processor upon activation of operation, said start-up program including steps for initializing said primary processor and steps for initializing common hardware elements usable by both said primary processor and secondary processor, said start-up program further including initialization code for said secondary processor, said secondary processor initialization code being comprised of a subset of operations comprising said start-up program and not including said steps for initializing said common hardware elements;
means for storing a redirection vector pointing to said secondary processor initialization code;
and
means for directing said secondary processor to utilize said redirection vector to execute said secondary processor initialization code.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/051,601Filed 22 Apr 1993 · continuation
Priority: 3 Nov 1989
Granted: 5 Mar 1996
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 11/1417
At system level: boot up procedures
G06F 9/4403
Bootstrapping: processor initialisation
G06F 9/4405
Bootstrapping: initialisation of multiprocessor systems
G06F 11/22
Error detection; Error correction; Monitoring: detection or location of defective computer hardware by testing during standby operation or during…