Superscalar processor controlling fetching of instructions based upon number of empty instructions registers detected for each cycle

A superscalar processor operating cyclically, comprising:

• a plurality of processing units provided in a parallel manner and capable of executing simultaneously provided instructions in a parallel manner;
• instruction storage means storing a plurality of instructions to be processed;
• fetch means, including a plurality of instruction registers, for reading a predetermined plurality of instructions from said instruction storage means and providing a multiple of the read predetermined plurality of instructions to the plurality of instruction registers;
• a decode means for decoding an instruction stored in each instruction register for each cycle and supplying the same to said plurality of processing units, said decoder means also selecting instructions which can be executed in a parallel manner and supplying the same to said plurality of processing units at the same time;
• and
• empty number detection means for detecting the number of empty instruction registers for each cycle,
• said fetch means further including control means for controlling providing the multiple of the read predetermined plurality of instructions to said plurality of instruction registers for each cycle in response to the detected number of empty instruction registers.