High byte right-shift apparatus with a register alias table

A microprocessor comprising:

• a bus interface unit for interfacing with a bus;
• an instruction decode and fetch unit coupled to said bus interface unit for decoding a current set of speculative operations for a given cycle;
• a plurality of execution units coupled to said instruction decode and fetch means for simultaneously executing the decoded operations;
• and
• means for renaming a current set of logical registers specified by a current set of operations to a current set of physical registers of an extended register set, said
• means for renaming for renaming said logical registers to said physical registers, wherein said means for renaming renames said logical registers to either a non-speculative state or a speculative state type of physical register, wherein said logical registers and said physical registers include larger width registers having partial width registers, wherein said partial width registers may include non right-adjusted partial width registers, said means for renaming for renaming a first logical register to a first physical register;
• and
• right-shifting means, coupled to said means for renaming and to said physical registers, for right-shifting a first datum of said first physical register into the least significant position of a second datum when said first logical register is a non right-adjusted partial width register and said first physical register is of said non-speculative state type.

A microprocessor comprising:

• a bus interface unit for interfacing with a bus;
• an instruction decode and fetch unit coupled to said bus interface unit for decoding a current set of operations for a given cycle;
• a plurality of execution units coupled to the instruction decode and fetch unit for simultaneously executing the decoded operations;
• and
• a renaming circuit coupled to said instruction decode and fetch unit, said renaming circuit for renaming a set of logical registers specified by a current set of operations to a current set of physical registers of an extended register set, said renaming circuit including,
• a reservation station for renaming said logical registers to said physical registers by storing rename values corresponding to said physical registers in reservation station locations associated with said logical registers, wherein said a reservation station renames said logical registers to either a non-speculative state or a speculative state type of physical register, wherein said logical registers and said physical registers include larger width registers having partial width registers, wherein said partial width registers may include non right-adjusted partial width registers, said reservation station for renaming a first logical register to a first physical register;
• and
• a right-shift circuit, coupled to said reservation station and to said physical registers, for right-shifting a first datum of said first physical register into the least significant position of a second datum when said first logical register is a non right-adjusted partial width register and said first physical register is of said non-speculative state type.

A computer system comprising:

• bus means for providing a communication interface;
• memory means coupled to said bus means for storing instructions and computer data;
• interface means coupled to said bus means for providing data input and data output to interlace with a user;
• and
• microprocessor means coupled to said bus means for executing said instructions and processing said computer data, said microprocessor means having a means for renaming a set d logical registers associated with a current set of operations to a current set of physical registers, said renaming means including,
• reservation station means for renaming said logical registers to said physical registers, wherein said reservation station means renames said logical registers to either a non-speculative state or a speculative state type of physical register, wherein said logical registers and said physical registers include larger width registers having partial width registers, wherein said partial width registers may include non right-adjusted partial width registers, said reservation station means renaming a first logical register to a first physical register;
• and
• right-shifting means, coupled to said reservation station means and to said physical registers, for right-shifting a first datum of said first physical register into the least significant position of a second datum when said first logical register is a non right-adjusted partial width register and said first physical register is of said first non-speculative state type.

A computer system comprising:

• a bus for providing communication interface;
• a memory coupled to said bus for storing instructions and computer data;
• an interface circuit coupled to said bus for providing data input and data output to interface with a user;
• and
• a microprocessor coupled to said bus means for executing said instructions and processing said computer data, said microprocessor having a renaming mechanism for renaming a set of logical registers associated with a current set of operation to a current set of physical registers, said renaming mechanism including,
• a reservation station for renaming said logical registers by storing rename values corresponding to said physical registers in the reservation station locations associated with said logical registers, wherein said reservation station renames said logical registers to either a non-speculative state or a speculative state type of physical register, wherein said logical registers and said physical registers include larger width registers having partial width registers, wherein said partial width registers may include non right-adjusted partial width registers, said reservation station for renaming a first logical register to a first physical register;
• and
• a right-shift circuit, coupled to said array memory and to said physical registers, for right-shifting a first datum of said first physical register into the least significant position of a second datum when said first logical register is a non right-adjusted partial width register and said first physical register is of said non-speculative state type.