Data processor in which external sync signal may be selectively inhibited

A single-chip microcomputer comprising:

• a central processing unit;
• external terminals for input and output of signals;
• a sync signal generation circuit for generating a clock signal as a sync signal;
• a control register holding a control bit having a set state or a clear state determined by the central processing unit, where the set state enables the supply of the sync signal to the one of the external terminals and the clear state inhibits the supply of the sync signal to said one of the external terminals;
• and
• a gate circuit coupled between the sync signal generation circuit and said one of the external terminals for coupling the sync signal generation circuit to said one of the external terminals when said control bit is in the set state, and for uncoupling the sync signal generation circuit from said one of the external terminals when the control bit is in the clear state.

A single-chip microcomputer including a central processing unit and a plurality of first external terminals for input or output signals, the single-chip microcomputer comprising:

• a second external terminal;
• sync signal generation means for generating a clock signal as a sync signal;
• a control register holding a control bit having a set state and a clear state, which are determined by the central processing unit, where the set state enables the supply of the sync signal to the second external terminal, and the clear state inhibits the supply of the sync signal to the second external terminal;
• and
• means for coupling the sync signal generation circuit to the second external terminal when said control bit is in the set state, and for uncoupling the sync signal generation circuit from the second external terminal when the control bit is in the clear state;
• wherein the second external terminal is used for an input or output signal when the control bit is in the clear state.

A single-chip microcomputer including a central processing unit and a plurality of first external terminals for input or output signals, an address bus and a data bus comprising:

• a second external terminal;
• a sync signal generation circuit for generating a clock signal as a sync signal;
• a control register coupled to the central processing unit via the address and data buses and including a central bit having a set state and a clear state, which are determined by the central processing unit, where the set state enables the supply of the sync signal to the second external terminal, and the clear state inhibits the supply of the sync signal to the second external terminal;
• and
• gate means for coupled between the sync signal generation circuit and the second external terminal for coupling the sync signal generation circuit to the second external terminal when the control bit is in the set state, and for uncoupling the sync signal generation circuit from the second external terminal when the control bit is in the clear state;
• wherein the second external terminal is used for an input or output signal when the control bit is in the clear state.

A single chip microcomputer, comprising:

• a central processing unit;
• a plurality of external terminals for input and output of signals;
• a clock signal generation circuit which generates a clock signal;
• a control circuit which is coupled to the central processing unit and which produces a control signal having a first state when the central processing unit sets in the control circuit first data and a second state when the central processing unit sets in the control circuit second data, wherein the first data indicates supply of the generated clock signal as a sync signal at one of the plurality of external terminals and the second data indicates inhibition of the supply of the generated clock signal at said one of the plurality of external terminals;
• and
• a gate circuit, which is coupled between the clock signal generation circuit and said one of the plurality of external terminals so as to couple the clock signal generation circuit to said one of the plurality of external terminals when the control signal is in the first state and to uncouple the clock signal generation circuit from said one of the plurality of external terminals when the control signal is in the second state.