Broadcast demap for deallocating memory pages in a multiprocessor system

An apparatus for removing an invalid page table entry from a plurality of translation lookaside buffers (TLBs) in a multiprocessor computer system having at least two processors coupled to a packet-switched bus, said invalid page table entry being specified by a virtual address and a process identification, said apparatus comprising:

• a first controller, coupled to said packet switched bus and a first one of said at least two processors, said first controller for broadcasting a demap request packet on said packet-switched bus in response to said first one of said at least two processors requesting that said invalid page table entry be removed from a first TLB controlled by said first controller, wherein said demap request packet comprises data specifying said virtual address and process identification of said invalid page table entry;
• and
• a second controller coupled to said packet-switched bus and a second one of said at least two processors, said second controller for receiving said demap request packet on said packet-switched bus, for sending a first demap reply packet on said packet-switched bus to said first controller to indicate that said second controller has received said demap request packet, for determining whether a second TLB controlled by said second controller contains said invalid page table entry by comparing said virtual address and said process identification to entries contained in said second TLB, for removing said invalid page table entry from said second TLB if said invalid page table entry is contained in said second TLB, and for sending a second demap reply packet on said packet-switched bus to said first controller after removal of said invalid page table entry from said second TLB to indicate that said second controller has processed said demap request packet, said second controller allowing said second one of said at least two processors to complete pending operations before said second controller removes said invalid page table entry from said second TLB.

A method for removing a page table entry from a plurality of cache memories in a multiprocessor computer system having at least two processors coupled to a packet-switched bus, the method comprising the steps of:

• broadcasting a demap request packet on the packet-switched bus by a first controller via a first bus watcher in response to a first one of the at least two processors requesting that the page table entry be removed from a first cache memory controlled by a first cache controller, the demap request packet including a virtual address and context information specifying the page table entry;
• receiving the demap request packet on the packet-switched bus by a second cache controller via a second bus watcher;
• sending a first demap reply packet on the packet-switched bus to the first cache controller via the first and second bus watchers by the second cache controller to indicate that the second cache controller has received the demap request packet;
• removing the page table entry from the second cache memory by the second cache controller if the page table entry is contained in the second cache memory;
• and
• sending a second demap reply packet on the packet-switched bus to the first cache controller via the second and first bus watchers by the second cache controller to indicate that the second cache controller has processed the demap request packet.