Memory access system and method modifying a memory interleaving scheme so that data can be read in any sequence without inserting wait cycles
AssigneeHewlett-Packard Company
InventorKoh Murata
Life of this patent
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Abstract
A memory access system and method is provided to modify a memory interleaving scheme so that data can be read from a memory system in any sequence without inserting a waiting cycle. Even addressees are assigned to a first memory bank and odd addresses to a second memory bank. If a sequential address sequence is being provided, the first and second memory banks are read alternately. A third memory bank is provided which has the contents of both first and second memory banks. When an address sequence is detected that successively accesses either the first memory bank or the second memory bank, the access is switched to the third memory bank.
Claims11
A memory system for outputting a sequence of digital words in response to a sequence of addresses comprising:
- a plurality of mutually independently operating memory banks for storing digital words, each said digital word being stored in association with an address of at least one of said plurality of memory banks;
- an auxiliary memory bank for storing a copy of at least some of said digital words stored within said plurality of memory banks, each of said at least some of said digital words being stored in association with an address of said auxiliary memory bank;
- means for selecting one memory bank from said plurality of memory banks and said auxiliary memory bank by selecting said auxiliary memory bank instead of one of said plurality of memory banks when two consecutive addresses of said sequence of addresses are associated with a single one of said plurality of memory banks;
- and
- access means for accessing a digital word stored in said one memory bank in accordance with a current address of said sequence of addresses.
A method of outputting a sequence of digital words in response to a sequence of addresses comprising:
- storing said sequence of digital words in a plurality of memory banks, each said digital word being stored in association with an address of at least one of said plurality of memory banks the memory banks being accessed in an interleaving manner;
- storing at least some of said digital words in an auxiliary memory bank, each of said at least some of said digital words being stored in association with an address of said auxiliary memory bank;
- selecting one memory bank from said plurality of memory banks and said auxiliary memory bank by selecting said auxiliary memory bank instead of one of said plurality of memory banks when two consecutive addresses of said sequence of addresses are associated with a single one of said plurality of memory banks;
- accessing a digital word stored in said one memory bank according to a current address of said sequence of addresses;
- and
- outputting each digital word so accessed from said one memory bank.
A memory system for outputting a sequence of digital words with a constant interval between any two consecutive digital words in response to a sequence of addresses comprising:
- a plurality of mutually independently operating memory banks for storing digital words, each said digital word being stored in association with an address of at least one of said plurality of memory banks;
- an auxiliary memory bank for storing a copy of at least some of said digital words stored within said plurality of memory banks, each of said at least some of said digital words being stored in association with an address of said auxiliary memory bank;
- selecting means for selecting one memory bank from said plurality of memory banks and said auxiliary memory bank by selecting said auxiliary memory bank instead of one of said memory banks if the time between consecutive accesses to said one memory bank does not exceed a predetermined time;
- and
- access means for accessing one of said digital words stored in said one memory bank in accordance with a current address of said sequence of addresses.
A method of outputting a sequence of digital words with a constant interval between consecutive digital words in response to a sequence of addresses comprising:
- storing said sequence of digital words in a plurality of memory banks, each said digital word being stored in association with an address of at least one of said plurality of memory banks, the memory banks being accessed in an interleaving manner;
- storing at least some of said digital words in an auxiliary memory bank, each of said at least some of said digital words being stored in association with an address of said auxiliary memory bank;
- selecting one memory bank from said plurality of memory banks and said auxiliary memory bank, said auxiliary memory bank being selected instead of one of said memory banks if the time between consecutive accesses to said one memory bank does not exceed a predetermined time;
- and
- accessing a digital word stored in said one memory bank according to a current address, said one memory bank outputting said digital word in response to said accessing.
Dependencies are inferred from the claim text.