Configurable integrated circuit having true and shadow EPROM registers

A configurable integrated circuit, comprising:

• a first set of N nonvolatile memory cells, where N is a positive integer greater than one, said first set of N nonvolatile memory cells for storing N binary configuration values;
• a second set of N nonvolatile memory cells for storing the boolean complements of said N binary configuration values;
• N configuration value sensing circuits, each configuration value sensing circuit coupled to one nonvolatile memory cell in said first set of N nonvolatile memory cells and a corresponding one nonvolatile memory cell from said second set of N nonvolatile memory cells, each configuration value sensing circuit outputting a configuration signal corresponding to the binary configuration value stored in said one nonvolatile memory cell in said first set of N nonvolatile memory cells;
• a multiplicity of configurable circuits, each configurable circuit having at least one circuit device that receives one of said configuration signals wherein each of said configurable circuits are configured in accordance with said one of said configuration signals received thereby;
• and
• power connections for coupling said integrated circuit to a supply voltage:
• wherein said first and second sets of N nonvolatile memory cells together enable said N configuration value sensing circuits to accurately sense said N binary configuration values when said supply voltage is as low as 2.5 volts.

A configurable integrated circuit, comprising:

• a first set of N nonvolatile memory cells, where N is a positive integer greater than one, said first set of N nonvolatile memory cells for storing N binary configuration values;
• a second set of N nonvolatile memory cells for storing the boolean complements of said N binary configuration values;
• N configuration value sensing circuits, each configuration value sensing circuit coupled to one nonvolatile memory cell in said first set of N nonvolatile memory cells and a corresponding one nonvolatile memory cell from said second set of N nonvolatile memory cells, each configuration value sensing circuit outputting a configuration signal corresponding to the binary configuration value stored in said one nonvolatile memory cell in said first set of N nonvolatile memory cells;
• each of said N configuration value sensing circuits including a latch having two internal nodes, one of which develops a low voltage and the other of which develops a higher voltage in accordance with the binary configuration value stored in said one nonvolatile memory cell in said first set of N nonvolatile memory cells;
• said latch further including strengthening means for providing additional current to the one of said internal nodes which develops said higher voltage and delay circuitry for enabling said strengthening means only after said two internal nodes of said latch have already developed opposite voltage levels, said strengthening means thereby protecting said latch from having its state changed by alpha particle radiation;
• and
• a multiplicity of configurable circuits, each configurable circuit having at least one circuit device that receives one of said configuration signals wherein each of said configurable circuits are configured in accordance with said one of said configuration signals received thereby.

A configurable integrated circuit, comprising:

• a first set of N nonvolatile memory cells, where N is a positive integer greater than one, said first set of N nonvolatile memory cells for storing N binary configuration values;
• a second set of N nonvolatile memory cells for storing the boolean complements of said N binary configuration values;
• N configuration value sensing circuits, each configuration value sensing circuit coupled to one nonvolatile memory cell in said first set of N nonvolatile memory cells and a corresponding one nonvolatile memory cell from said second set of N nonvolatile memory cells, leach configuration value sensing circuit outputting a configuration signal corresponding to the binary configuration value stored in said one nonvolatile memory cell in said first set of N nonvolatile memory cells;
• each of said N configuration value sensing circuits including test circuitry for testing integrity thereof when both of said nonvolatile memory cells coupled thereto are unprogrammed, wherein said test circuitry is enabled only when a predetermined one nonvolatile memory cell in said first set of N nonvolatile memory cells and a corresponding predetermined one nonvolatile memory cell from said second set of N nonvolatile memory cells are in respective predefined storage states;
• and
• a multiplicity of configurable circuits, each configurable circuit having at least one circuit device that receives one of said configuration signals wherein each of said configurable circuits are configured for operation in accordance with said one of said configuration signals received thereby.