Control circuit for controlling a cache memory divided into a plurality of banks

A control circuit for controlling a cache memory which is separated from a main memory and which is divided into a plurality of banks, each bank having a tag memory and a data memory and said tag memory being constituted so as to output a reference address in response to an access signal, said circuit for controlling a cache memory comprising:

• a means for inputting an address signal comprising an index section and tag section in each of said banks via a first signal line for inputting the tag section and a second signal line for inputting the index section;
• a branch line for inputting the index section which is branched from said signal line for inputting the index section;
• an address delay means intervening in said branch line for inputting the index section so as to delay the output of the index section of the address signal;
• a signal switching means included in each of said banks, each of said switching means having the output connected to said tag memory and data memory of the associated bank and the input connected to the output of said second signal line for inputting the index section and to the output of the address delay means intervening in the branch line for inputting the index section, said signal switching means being constituted so as to switch output data between data which is inputted via the second signal line for inputting the index section and delayed data which is inputted via the branch line for inputting the index section;
• an address comparing means which is included in each of said banks and which has the input terminal connected to said first signal line for inputting the tag portion and to the output signal line of said tag memory of the associated bank, so as to compare the tag section of said address signal with the reference address output from said tag memory of the associated bank and to output an coincidence signal when there is a coincidence between the two;
• a writing-operation control means which fetches, when the coincidence signal is outputted from one of said banks, a memory corresponding to said address from the main memory and controls the writing of data in the data memory of the bank in which said coincidence signal was outputted;
• and
• a means for selectively controlling operations which controls said switching means so that, when the coincidence signal is outputted from said address comparing means in view of the results of comparison which was made by the address comparing means for writing, the delayed data of the index section of the address signal is selected as the access signal for the next comparison to be outputted to said memory tag.