High performance computer system which minimizes latency between many high performance processors and a large amount of shared memory

A machine design for a high performance computer system which minimizes latency between many high performance processors and a large amount of shared memory comprising:

• a plurality of generally rectangular edge-connected modules, each of said edge connected modules being characterized by signal input/output pads on three edges, first and second opposing edges being referred to as inside connector edges and a third edge being referred to as a global connector edge, said edge-connected modules being configured as processor edge-connected modules, basic storage module edge-connected modules, and request and response switch edge-connected modules;
• a plurality of stacks of modules, each stack comprising a group of processor edge-connected modules, a group of request switch edge-connected modules, a group of basic storage module edge-connected modules, and a group of respond switch edge-connected modules;
• said groups being arranged within each of said stacks such that said group of processor modules is separated on one end from said basic storage modules by said group of respond switch modules and on the other end from said basic storage modules by said group of said request switch modules so that data flow from a processor through a request switch to an addressed basic storage module and through a respond switch back to the processor is unidirectional about a first loop defined by connections on the inside edges of the edge-connected modules;
• and
• said groups being further arranged about said loop so that parallel delay times within groups is equal, and propagation time about said first loop is an integral number of processor cycle times, each of said stacks being interconnected with the other stacks of modules via global wiring connected to global connector edges of said modules in a second loop such that processor modules in said first stack are connected to request switch modules which are connected in turn to basic storage modules in one of said other stacks which are connected in turn to respond switch modules which are connected in turn back to said processor modules in said first stack, each stack being a mirror image of the adjacent stack so as to minimize said global wiring.

A machine design for a high performance computer system which minimizes latency between many high performance processors and a large amount of shared memory comprising:

• stacks of generally rectangular edge-connected modules arranged in at least one set of joined pairs, each joined pair in said at least one set of joined pairs comprising a pair of joined stacks, each of said edge connected modules being characterized by signal input/output pads on three edges, first and second opposing edges being referred to as inside connector edges and a third edge being referred to as a global connector edge, said edge-connected modules being configured as processor edge-connected modules, basic storage module edge-connected modules, and request and response switch edge-connected modules;
• a group of processor edge-connected modules and a group of request or respond switch edge-connected modules stacked in a first stack of each joined pair, and a group of basic storage module edge-connected modules and a group of respond or request switch edge-connected modules stacked in a second stack of each joined pair;
• said first and second stacks of each joined pair being arranged adjacent one another with the group of request or respond switch edge connected modules above or below the group of processor edge-connected modules in said first stack and the group of respond or request switch edge-connected modules below or above the group of basic storage module edge-connected modules in said second stack so that the group of respond or request switch edge-connected modules are adjacent the group of processor edge-connected modules of the first stack and the group of request or respond switch edge-connected modules are adjacent the group of basic storage module edge-connected modules of the second stack to form a first joined pair of said one set of joined pairs, said first joined pair comprising a pair of joined stacks having processor modules connected to request switch modules connected to basic storage modules connected to respond switch modules connected back to said processor modules in a first loop;
• connection means connecting processors in said first stack of said first joined pair through said request switches to addressed basic storage modules in said second stack of said first joined pair and through said respond switches back to the processor providing a data flow path being unidirectional about said first loop defined by connections on both inside edges of the edge-connected modules;
• a second joined pair in said at least one set of joined pairs which is a mirror image of said first joined pair;
• and
• wherein first and second joined pairs of said at least one set of joined pairs are stacked adjacent one another;
• global connectors interconnecting said first and second joined pairs to the third edges of the edge-connected modules, the global connectors allowing processors of said first joined pair to be connected to request switch modules of either said first or second joined pair, to in turn be connected to basic storage modules of said second joined pair, to in turn be connected to respond switch modules of either said first or second joined pair, to in turn be connected back to said processor of said first joined pair in a second loop while minimizing connection wiring length in said interconnection means.