Dynamic address translation allowing quick update of the change bit

A virtual memory data processing system comprising:

• a main memory for storing an address conversion table;
• and
• a central processing unit for performing a dynamic address translation operation to translate a virtual address to a real address by referring to the address conversion table, said central processing unit comprising:
• first storage means for holding a prior translated virtual address;
• second storage means for holding a table entry of the address conversion table corresponding to the virtual address held in the first storage means, said table entry having an update bit indicating that the memory has been written to;
• third storage means for holding the real address of the table entry held in the second storage means;
• comparison means for comparing the prior translated virtual address held in the first storage means with a virtual address to be translated to a real address;
• and
• update means for changing contents of the update bit in the table entry held in the second storage means when the virtual memory has been written to, wherein when the virtual address coincides with the other virtual address in the comparison circuit, the table entry changed by the update means is written into an address of the main memory held in the third storage means.