US 5,497,459 AGranted

System for testing instruction queue circuit and central processing unit having the system

AssigneeFujitsu Limited

InventorsHisamitsu Tanihira, Renri Nakano, Kazuo Nagahori

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Abstract

In a system for testing an instruction queue circuit connected to an external memory via a bus controller provided in a processor having a microprogram control unit, an operation unit connected to the microprogram control unit and connected, via an internal bus, to the instruction queue circuit, the instruction queue circuit-including a plurality of queue buffers, a writing unit writes internal bus information transferred via the internal bus into the instruction queue circuit in response to a first instruction generated by the microprogram control unit. The internal bus information is contained in the first instruction. A reading unit reads the internal bus information from the instruction queue circuit in response to a second instruction generated by the microprogram control unit. A gate circuit outputs the internal bus information to the internal bus in response to a third instruction generated by the microprogram control circuit. The internal bus information is used to test the instruction queue circuit.

Claims8

Dependent claims

A system for testing an instruction queue circuit provided in a data processor and being connected to an external memory via a bus controller of the processor which further has a microprogram control unit which generates a first instruction, a second instruction and a third instruction prefetched in said processor, an operation unit connected to the microprogram control unit and to the instruction queue circuit via an internal bus wherein the instruction queue circuit includes a plurality of queue buffers for temporarily storing said first and second prefetched instructions, said testing system comprising:

writing means, coupled to the instruction queue circuit and the microprogram control unit, for writing internal bus information transferred via the internal bus and used to test the instruction queue circuit into the instruction queue circuit in response to said first instruction generated by the microprogram control unit;
reading means, coupled to the instruction queue circuit and the microprogram control unit, for reading the internal bus information from the instruction queue circuit in response to said second instruction generated by the microprogram control unit;
gate means, coupled to said microprogram control unit and said instruction queue circuit, for connecting said instruction queue circuit to said internal bus and for outputting the internal bus information read from said instruction queue circuit to the internal bus in response to said third instruction generated by the microprogram control circuit,
the first, second and third instructions and the internal bus information being generated in the microprogram control unit by decoding microinstructions in the microprogram control unit;
and
selecting means, coupled directly to the microprogram control unit and the instruction queue circuit and also coupled to said internal bus and an instruction bus, for selecting either the internal bus or the instruction bus to be coupled to the external memory via the bus controller in response to a fourth instruction generated by the microprogram control unit and for connecting a selected bus to the instruction queue circuit so as to switch said instruction queue circuit to an operation mode or a testing mode.

3 more elements

A data processor comprising:

a microprogram control unit for generating a first instruction, a second instruction and a third instruction, said first, second and third instructions being prefetched;
an instruction queue circuit connected to an external memory via a bus controller and being coupled to said microprogram control unit and including a plurality of queue buffers for temporarily storing said first and second prefetched instructions;
an operation unit connected to the microprogram control unit and which is also connected, via an internal bus, to the instruction queue circuit;
writing means, coupled to the instruction queue circuit and the microprogram control unit, for writing internal bus information transferred via the internal bus and used for testing the instruction queue circuit into the instruction queue circuit in response to said first instruction generated by the microprogram control unit;
reading means, coupled to the instruction queue circuit and the microprogram control unit, for reading the internal bus information from the instruction queue circuit in response to said second instruction generated by the microprogram control unit;
gate means, coupled to the microprogram control unit and said instruction queue circuit for connecting said instruction queue circuit to said internal bus and for outputting the internal bus information read from said instruction queue circuit to the internal bus in response to said third instruction generated by the microprogram control unit,
wherein the microprogram control unit comprises:
a micro-ROM storing microinstructions;
and
decoder means, coupled to the micro-ROM, for decoding the microinstructions received from said micro-ROM and generating control signals from said microinstructions,
said first, second and third instructions corresponding to the control signals;
and
selecting means, coupled directly to the instruction queue circuit and the microprogram control unit and also coupled to the internal bus and an instruction bus, for selecting either the internal bus or the instruction bus to be coupled to the external memory via the bus controller in response to a fourth instruction generated by the microprogram control unit and for connecting a selected bus to the instruction queue circuit so as to switch said instruction queue circuit to an operation mode or a testing mode.

10 more elements

Dependencies are inferred from the claim text.