Cache testability circuit for embedded diagnostics

A computer system which performs cache memory diagnostics, comprising:

• a CPU;
• cache memory coupled to the CPU;
• a cache controller coupled to the CPU and the cache memory;
• main memory;
• a memory controller coupled to the main memory, the CPU, and the cache controller;
• a buffer coupled between the memory controller and the main memory which receives a write signal from the memory controller and provides said write signal to the main memory;
• and
• a signal source coupled to said buffer and the CPU which asserts a disable signal to said buffer during cache memory diagnostics, wherein said disable signal prevents assertion of said write signal to the main memory during said cache memory diagnostics but does not prevent assertion of read signals to the main memory during said cache memory diagnostics.

A method for performing cache memory diagnostics in a computer system comprising a CPU, a cache system coupled to the CPU including cache memory and a cache controller, main memory, and a memory controller coupled to the main memory, the CPU, and the cache controller, wherein the memory controller does not allow hits to the cache memory involving memory addresses corresponding to a non-cacheable address space, and a buffer coupled between the memory controller and the main memory which receives a write signal from the memory controller and provides said write signal to the main memory, the method comprising:

• disabling write operations to, but not read operations from, the main memory by disabling operation of said buffer;
• loading tag addresses into the cache system;
• and
• testing the cache memory after performing said steps of disabling and loading.