Method and apparatus for selectable parallel execution of test operations

A method of synchronizing operations of a plurality of logic circuits, comprising the steps of:

• providing a plurality of connection ports connected to a control bus for connecting logic circuits to the control bus in response to addresses presented to the connection ports via the control bus;
• presenting to the connection ports a first address associated with a first said connection port so that a first logic circuit associated with the first connection port is connected to the control bus while the remaining logic circuits, whose associated connection ports are not currently addressed, remain disconnected from the control bus, and thereafter withdrawing the first address from the connection ports without addressing any of the connection ports so that the first logic circuit is disconnected from the control bus without connecting any of the remaining logic circuits to the control bus;
• and
• changing a control state of the control bus after said step of withdrawing the first address, so that the control state is changed while the logic circuits are all disconnected from the control bus.