Synchronous address latching for memory arrays
AssigneeIntel Corporation
InventorsDuane R. Mills, Richard Fackenthal, Rod Rozman, Mamun Rashid
Life of this patent
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Abstract
Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has first and second master latches to receive and store an external address. A first slave latch is also included to receive and store the external address from the first master latch if the external address belongs to the first bank and to provide the external address as a first address to the first bank. A second slave latch is included to receive and store the external address from the second master latch if the external address belongs to the second bank and to provide the external address as a second address to the second bank.
Claims22
Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays, said latching circuitry comprising:
- a first master latch to receive and store an external address if the external address belongs to the first bank;
- a first slave latch to receive and store the external address from the first master latch and to provide a first slave output address, if the external address belongs to the first bank, the first slave latch to provide the external address to the first bank as the first slave output address;
- a first input multiplexer to receive the external address and to receive the first slave output address from the first slave latch, if the external address belongs to the first bank,-the first input multiplexer to provide the external address to the first master latch, if the external address does not belong to the first bank, the first input multiplexer to provide the first slave output address to the first master latch;
- a second master latch to receive and store the external address if the external address belongs to the second bank;
- a second slave latch to receive and store the external address from the second master latch and to provide a second slave output address, if the external address belongs to the second bank, the second slave latch to provide the external address to the second bank as the second slave output address;
- and
- a second input multiplexer to receive the external address and to receive the second slave output address from the second slave latch, if the external address belongs to the second bank, the second input multiplexer to provide the external address to the second master latch, if the external address does not belong to the second bank, the second input multiplexer to provide the second slave output address to the second master latch.
A method for synchronously latching addresses for a memory device having at least first and second banks of memory arrays, said method comprising the steps of:
- receiving an external address and output from a first slave latch as inputs to a first multiplexer;
- the first input multiplexer providing as output a first address to a first master latch, if the external address belongs to the first bank, the first address being the external address, if the external address does not belong to the first bank, the first address being the output of the first slave latch;
- the first master latch receiving and storing the first address;
- the first slave latch receiving and storing the first address from the first master latch and providing the first address to the first bank and to the first input multiplexer;
- receiving the external address and output from a second slave latch as inputs to a second multiplexer;
- the second input multiplexer providing as output a second address to a second master latch, if the external address belongs to the second bank, the second address being the external address, if the external address does not belong to the second bank, the second address being the output of the second slave latch;
- the second master latch receiving and storing the second address;
- the second slave latch receiving and storing the second address from the second master latch and providing the second address to the second bank and to the second input multiplexer.
Dependencies are inferred from the claim text.