Bit map addressing schemes for flash memory
AssigneeIntel Corporation
InventorsSherif Sweha, Mark E. Bauer
Life of this patent
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Abstract
Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.
Claims4
In a flash electrically erasable programmable read-only memory circuit, a sense path circuit for selectively accessing data stored in one of a plurality of data blocks, each data block including at least one memory cell that stores n bits, wherein n is greater than 1, the sense path circuit comprising:
- a plurality of n outputs;
- a row decoder circuit coupled to the data blocks;
- a first column decode circuit coupled to a first memory cell of a first data block for addressing the first memory cell in conjunction with the row decoder circuit in response to an address;
- a second column decode circuit coupled to a first memory cell of a second data block for addressing the first memory cell of the second data block in conjunction with the row decoder circuit in response to the address;
- a sensing circuit for determining each of the n bits stored in a selected memory cell and for outputting each of the n bits to a corresponding one of the n outputs;
- and
- a selector circuit for selectively coupling either the first memory cell of the first data block or the first memory cell of the second data block to the sensing circuit in response to a select signal.
A flash electrically erasable programmable read-only memory device comprising:
- a plurality of inputs including row address inputs, column address inputs, and at least one select input;
- a memory cell array arranged in a plurality of rows and columns, the memory cell array comprising a plurality of m data blocks, each data block comprising a plurality of memory cells, wherein each memory cell is operative to store n bits of data;
- wherein n is greater than 1;
- a row decoder circuit coupled to the plurality of m data blocks, wherein the row decoder circuit selects a row of the memory cell array in response to a row address received via the row address inputs;
- a plurality of m column decoder circuits each coupled to a corresponding one of the plurality of m data blocks, wherein each column decoder circuit selects a column of the corresponding data block in response to a column address received via the column address inputs such that m memory cells are selected for reading in response to the row and column addresses;
- a plurality of m/n sensing circuits each for determining the n bits of one of n selected memory cells;
- a plurality of m outputs coupled to the plurality of sensing circuits for outputting data sensed by the plurality of sensing circuits;
- and
- a selector circuit coupled to the plurality of column decoder circuits and the plurality of sensing circuits for selectively coupling m/n of the m selected memory cells to the plurality of m/n sensing circuits in response to a selected signal carried by the select input.
Dependencies are inferred from the claim text.