US 5,497,352 A · Semiconductor memory device having dual mode operation

Abstract

An improvement of a semiconductor memory device capable of designating a block write mode in which writing is effected simultaneously to a plurality of memory cells unitized by predetermined numbers and connected respectively to a plurality of column lines. Data lines correspond to a predetermined number of memory cells. The data lines and the column lines are selectively connected to each other by switches. During a block write mode, a predetermined number of column lines are simultaneously connected to the data lines corresponding thereto. During the other mode, a control unit controls the switches to connect some of the predetermined number of column liens to the data lines corresponding thereto. During the mode other than the block write mode, only a part of the predetermined number column lines are connected to the data lines, thereby reducing electric power consumption.

Claims21

Dependent claims

A semiconductor memory device operable in a first mode and a second mode, comprising:

a memory cell array having a plurality of memory cells arranged in a matrix form and having a plurality of column lines connected to the memory cells in a same column, said memory cells and said column lines being divided into a plurality of column blocks;
a plurality of data lines;
a plurality of switch means each connected between a corresponding one of the column lines and one of the data lines;
a column address buffer circuit for generating a first group of address signals and a second group of address signals;
a buffer circuit connected to the plurality of data lines, said buffer circuit receiving the first group of address signals and selectively amplifying data on the data lines;
a first column decoder circuit configured to receive the first group of address signals and to generate subaddress signals, said subaddress signals being partially activated in the first mode and being wholly activated in the second mode;
and
a second column decoder circuit configured to receive the subaddress signals and the second group of address signals and to generate column selection signals for controlling said plurality of switch means.

5 more elements

The semiconductor memory device operable in a first mode and a second mode, comprising:

a memory cell array having a plurality of memory cells arranged in a matrix form and having a plurality of bit line pairs, the memory cells in a same column being connected to a corresponding one of the bit line pairs, the plurality of bit line pairs being divided into a plurality of first groups each having N bit line pairs, each of the first groups being divided into a plurality of second groups each having M bit line pairs;
a data bus having N data line pairs, each of the N data line pairs corresponding to a different one of the bit line pairs in the first groups;
a plurality of switch means each connected between a bit line pair and a corresponding data line pair;
a plurality of column select lines each connected to a switch means in one of the second groups;
a buffer circuit connected to the data bus for amplifying data on the data bus;
and
decoding means for receiving address signals and for selectively activating the column select lines, the decoding means activating the column select lines belonging to one of the first groups in the first mode, and activating the column select lines belonging to one of the second groups in the second mode.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device having dual mode operation

Life of this patent

Semiconductor memory device having dual mode operation

Life of this patent

Abstract

Claims21