Dynamic random access memory device having first and second I/O line groups isolated from each other

A dynamic random access memory device comprising:

• a memory cell array including a plurality of memory blocks each having a plurality of memory cells provided at crossing points between word lines and bit lines extending substantially perpendicular to each other, each of said memory blocks including a first memory block part and a second memory block part portioned in a first direction parallel with said bit lines, the bit lines in any one of said memory blocks being isolated from the bit lines in other ones of said memory blocks;
• a plurality of column switches, one provided for each of said bit lines in each of said memory blocks;
• a predetermined number of first input/output lines provided for each of said first and second memory block parts of each of said memory blocks, each of said predetermined number of first input/output lines being connected to different ones of said bit lines via associated ones of said column switches in each of said memory blocks, said predetermined number of first input/output lines for said first memory block part and said predetermined number of first input/output lines for said second memory block part extending in a second direction parallel with said word lines and being isolated from each other in each of said memory blocks;
• a row address decoder for decoding a first portion of an address signal to generate a word line selection signal to be applied to one of said word lines and a column address decoder for decoding a second portion of said address signal to generate a bit line selection signal to be applied to at least one of the column switches for the bit lines in each of said first memory block part and said second memory block part of one of said memory blocks to thereby simultaneously access at least two memory cells in said one memory block with said address signal to transfer data signals between said at least two memory cells and said predetermined number of first input/output lines for the first and second memory block parts of said one memory block, the number of said memory cells to be simultaneously accessed being the same as said predetermined number;
• a first input/output gate circuit including a plurality of first input/output gates, one first input/output gate being provided for each of said memory blocks, the first input/output gate associated with each of said memory blocks being connected to said predetermined number of first input/output lines for the first memory block part of the memory block, and a second input/output gate circuit including a plurality of second input/output gates, one second input/output gate being provided for each of said memory blocks, the second input/output gate associated with each of said memory blocks being connected to said predetermined number of first input/output lines for the second memory block part of the memory block;
• a switch control circuit for producing, on a basis of said signal address a control signal for controlling said first and second input/output gate circuits, said switch control circuit being electrically connected in common to said first and second input/output gate circuits so that the first input/output gate and the second input/output gate of a respective memory block are simultaneously closed;
• a predetermined number of second input/output lines connected in common to said first input/output gates, and a predetermined number of third input/output lines connected in common to said second input/output gates;
• and
• first main amplifiers connected to said second input/output lines and second main amplifiers connected to said third input/output lines, said first and second input/output gates for each of said memory blocks, when simultaneously closed by said control signal, serving to transfer data signals between the first input/output lines for the first memory block part of the memory block and said second input/output lines and transfer data signals between the first input/output lines for the second memory block part of the memory block and said third input/output lines so that said data signals on said second and third input/output lines are amplified by said first and second main amplifiers, respectively.