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US 5,497,347 AGranted
BICMOS cache TAG comparator having redundancy and separate read an compare paths
AssigneeMotorola, Inc.
InventorTaisheng Feng
Life of this patent
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Abstract
A cache TAG comparator (20) has a combined data multiplexer and compare circuit (30) for multiplexing redundant columns (26) with normal columns of memory cells and for comparing input data with a TAG address stored in a TAG array (21) for determining if data required by a data processing system is located in a corresponding cache memory. A BICMOS match logic circuit (40) receives a compare signal from each data multiplexer and compare circuit, and provides a logic high match signal indicating a cache hit in response to a logic state of the input data and the TAG address being identical. The comparison is performed in ECL, allowing high speed operation. Also, the match signal is generated prior to a critical read path, insuring faster generation of the match signal.
Claims20
A cache TAG comparator, comprising:
- a TAG array of memory cells;
- a redundant array of memory cells for replacing defective memory cells of the TAG array;
- a plurality of data multiplexers, coupled to the TAG array and to the redundant array, a data multiplexer of the plurality of data multiplexers providing a TAG address bit having a logic state corresponding to the logic state of a selected one of the memory cells of either of the TAG array and the redundant array;
- a plurality of comparators, coupled to the plurality of data multiplexers, a comparator of the plurality of comparators coupled to a data multiplexer of the plurality of data multiplexers, the comparator receiving the TAG address bit and an input data bit, and providing a compare signal at an output terminal of a first logic state if the logic state of the TAG address bit is the same as a logic state of the input data bit, and providing the compare signal at a second logic state if the logic state of the TAG address bit is not the same as the logic state of the input data bit;
- and
- a BICMOS match logic circuit, coupled to the plurality of comparators, the BICMOS match logic circuit providing a match signal having the first logic state if all of the compare signals are a same logic state, and providing the match signal at the second logic state if all of the compare signals are not the same logic state.
3 more elements
A cache TAG comparator, comprising:
- a TAG memory array for providing a predetermined number of TAG address bits in response to receiving an address;
- a plurality of local sense amplifiers, a local sense amplifier of the plurality of local sense amplifiers having an input terminal coupled to the TAG memory array for receiving one TAG address bit of the predetermined number of TAG address bits, and an output terminal;
- a plurality of comparators, a comparator of the plurality of comparators having a first input terminal coupled to the output terminal of the local sense amplifier, a second input terminal for receiving an input data bit of a plurality of input data bits, the comparator comparing a logic state of the one TAG address bit to a logic state of the input data bit, the comparator having an output terminal for providing a compare signal of a first logic state if the logic state of the one TAG address bit is the same as the logic state of the input data bit, and the comparator providing the compare signal at a second logic state if the logic state of the one TAG address bit is not the same as the logic state of the input data bit;
- and
- a BICMOS match logic circuit having a plurality of input terminals, each input terminal of the plurality of input terminals directly coupled to the output terminal of each comparator of the plurality of comparators, the BICMOS match logic circuit for comparing the compare signals of the plurality of comparators, and the BICMOS match logic circuit having an output terminal for providing a match signal if the compare signals from the plurality of comparators are the same logic state.
2 more elements
A cache TAG comparator, comprising:
- an array of memory cells arranged in intersecting rows and columns, the array for storing a TAG address of a predetermined number of bits, the array providing the TAG address of the predetermined number of bits in response to receiving an address;
- a plurality of redundant columns of memory cells, a redundant column of memory cells for replacing a defective column of the array;
- a plurality of local sense amplifiers of the predetermined number, a local sense amplifier of the plurality of local sense amplifiers having an input terminal coupled to the array of memory cells, and an output terminal for providing a TAG address bit signal corresponding to a TAG address bit of the predetermined number of bits;
- a redundant local sense amplifier having an input terminal coupled to the plurality of redundant columns of memory cells, and an output terminal for providing a redundant TAG address bit signal if a redundant column has replaced a defective column of the array;
- a plurality of data multiplexing and compare circuits of the predetermined number, a data multiplexing and compare circuit of the plurality of data multiplexing and compare circuits having a first input terminal for receiving the TAG address bit signal, a second input terminal coupled to the redundant local sense amplifier for receiving the redundant TAG address bit signal, a third input terminal for receiving an input data signal, the data multiplexing and compare circuit for comparing either the TAG address bit signal or the redundant TAG address bit signal to the input data signal in response to a redundant control signal, the data multiplexing and compare circuit having an output terminal for providing a compare signal of a first logic state if a logic state of the TAG address bit signal or the redundant TAG address bit signal is the same as a logic state of the input data signal, and the data multiplexing and compare circuit providing the compare signal at a second logic state if the logic state of the TAG address bit signal or the redundant TAG address bit signal is not the same as the logic state of the input data signal;
- and
- a BICMOS match logic circuit having a plurality of input terminals, each of the plurality of input terminals coupled to the output terminal of each of the plurality of data multiplexing and compare circuits, the BICMOS match logic circuit having an output terminal for providing a match signal if the compare signals of the plurality of data multiplexing and compare circuits are the same logic state.
4 more elements
Dependencies are inferred from the claim text.