Semiconductor memory device
AssigneeOki Electric Industry Co., Ltd.
InventorNoboru Egawa
Life of this patent
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Abstract
An object of the present invention is to provide a semiconductor memory device capable of reducing a delay in the transmission of a chip select signal, which is developed inside a chip and providing very fast access times for chip selection. A chip select terminal to which a chip select signal is externally supplied, is electrically connected to an inner conductive pattern. A first input circuit is disposed as a pre-stage circuit so as to be electrically connected to each of a plurality of inner circuits. The chip select signal supplied to the chip select terminal from the outside of the chip is directly transmitted to each of the first input circuits through the inner conductive pattern so as to be supplied to each of the inner circuits.
Claims23
A semiconductor memory device having at least one inner circuit, the device comprising:
- a chip select terminal for receiving a chip select signal from outside the device;
- an inner conductive pattern, directly electrically connected to said chip select terminal, for carrying the chip select signal;
- and
- at least one first input circuit, directly electrically connected to said inner conductive pattern and to said at least one inner circuit, for transmitting the chip select signal carried by said inner conductive pattern to said at least one inner circuit.
A semiconductor memory device having at least one inner circuit, the device comprising:
- a chip select terminal for receiving a chip select signal from outside the device;
- an inner conductive pattern, directly electrically connected to said chip select terminal, for carrying the chip select signal;
- and
- at least one first input circuit, disposed in the immediate neighborhood of said at least one inner circuit and directly electrically connected to said inner conductive pattern and to said at least one inner circuit, for transmitting the chip select signal carried by said inner conductive pattern to said at least one inner circuit.
A semiconductor memory device having a plurality of inner circuits, the device comprising:
- a chip select terminal for receiving a chip select signal from outside the device;
- an inner conductive pattern, directly electrically connected to said chip select terminal, for carrying the chip select signal;
- and
- a plurality of first input circuits, of a number corresponding to the plurality of inner circuits, each first input circuit being disposed in the immediate neighborhood of and being respectively directly electrically connected to a respective corresponding one of said plurality of inner circuits, each first input circuit for respectively transmitting the chip select signal carried by said inner conductive pattern to a respective corresponding one of said plurality of inner circuits.
Dependencies are inferred from the claim text.