US 5,497,341 A · Sign-extension of immediate constants in an ALU using an adder in an integer logic unit

Abstract

An arithmetic-logic unit (ALU) includes a Boolean logic unit and an integer logic unit, both of which are adapted to incorporate the sign extension function for immediate constants or reduced-width operands. The Boolean logic unit is constructed from 4:1 multiplexers (muxes), one mux for every bit in a full-width operand. The operands or constants are input to the select inputs for the muxes while signals representing the truth table for a predetermined Boolean operation are inputted to the four data inputs of each of the muxes. This allows for many different kinds of Boolean operations to be executed by the Boolean logic unit; each type of Boolean operation called for by an instruction opcode will have a corresponding set of truth table signals for input to the muxes. Sign-extension can be combined with the Boolean operation by using the sign bit of the reduced-width operand to select one of two modified sets of truth-table signals. The selected set of truth-table signals is applied to the data inputs of the muxes. An upper section of the truth-table sets has the sign bit of the reduced width operand encoded into the truth-table sets themselves. The integer arithmetic unit uses exclusive-OR gates, controlled by the sign bit, to selectively invert the reduced width operand. The output, which is always a positive number, is extended with zeros, then selectively inverted again before being added to a second operand in an adder. Addition or subtraction incorporating the sign-extension of one operand is thus possible with the modified integer arithmetic unit.

Claims20

Dependent claims

An arithmetic unit for adding and subtracting binary numbers represented in two's complement format, the unit comprising:

a first operand input, the first operand input having a plurality of binary signals for representing a first operand as a binary number in two's complement format, the first operand having a sign bit for indicating if the first operand is a positive or a negative binary number;
a first inversion control input for enabling inversion of the plurality of binary signals representing the first operand, the first inversion control input receiving the sign bit for the first operand;
first inverting means, responsive to the first inversion control input, for selectively inverting each binary signal in the plurality of binary signals representing the first operand, the first inverting means producing a selectively inverted output;
extension means, receiving the selectively inverted output from the first inverting means, for extending the output with binary signals representing zero, the extension means producing a zero-extended result representing a positive number;
a second inversion control input, for enabling inversion of the zero-extended result;
second inverting means, responsive to the second inversion control input, for selectively inverting the zero-extended result, the second inverting means having an output;
a second operand input, the second operand represented as a binary number in two's complement format;
an adder, receiving the second operand and coupled to the output of the second inverting means, the adder calculating the sum of the second operand and the output of the second inverting means, the adder having a single-bit carry-in input for increasing the sum by one,
whereby addition and subtraction can be performed on operands without explicit sign extension.

6 more elements

An arithmetic unit for adding and subtracting binary numbers represented in two's complement format, the unit comprising:

a first operand input, the first operand input having a plurality of binary signals for representing a first operand as a binary number in two's complement format, the first operand having a sign bit for indicating if the first operand is a positive or a negative binary number;
a first inversion control input for enabling inversion of the plurality of binary signals representing the first operand, the first inversion control input receiving the sign bit for the first operand;
first inverting means, responsive to the first inversion control input, for selectively inverting each binary signal in the plurality of binary signals representing the first operand, the first inverting means producing a selectively inverted output;
an extender, receiving the selectively inverted output from the first inverting means, for extending the output with binary signals representing zero, the extender producing a zero-extended result representing a positive number;
a second inversion control input, for enabling inversion of the zero-extended result;
second inverting means, responsive to the second inversion control input, for selectively inverting the zero-extended result, the second inverting means having an output;
a second operand input, the second operand represented as a binary number in two's complement format;
an adder, receiving the second operand and coupled to the output of the second inverting means, the adder calculating the sum of the second operand and the output of the second inverting means, the adder having a single-bit carry-in input for increasing the sum by one,
whereby addition and subtraction can be performed on operands without explicit sign extension.

6 more elements

An arithmetic unit for adding and subtracting binary numbers represented in two's complement format, the unit comprising:

a first operand input, the first operand input having a plurality of binary signals for representing a first operand as a binary number in two's complement format, the first operand having a sign bit for indicating if the first operand is a positive or a negative binary number;
a first inversion control input for enabling inversion of the plurality of binary signals representing the first operand, the first inversion control input receiving an inverse of the sign bit for the first operand;
first inverting means, responsive to the first inversion control input, for selectively inverting each binary signal in the plurality of binary signals representing the first operand, the first inverting means producing a selectively inverted output;
an extender, receiving the selectively inverted output from the first inverting means, for extending the output with binary signals representing ones, the extender producing a ones-extended result representing a negative number;
a second inversion control input, for enabling inversion of the ones-extended result;
second inverting means, responsive to the second inversion control input, for selectively inverting the ones-extended result, the second inverting means having an output;
a second operand input, the second operand represented as a binary number in two's complement format;
an adder, receiving the second operand and coupled to the output of the second inverting means, the adder calculating the sum of the second operand and the output of the second inverting means, the adder having a single-bit carry-in input for increasing the sum by one,
whereby addition and subtraction can be performed on operands without explicit sign extension.

6 more elements

Dependencies are inferred from the claim text.

Sign-extension of immediate constants in an ALU using an adder in an integer logic unit

Life of this patent

Sign-extension of immediate constants in an ALU using an adder in an integer logic unit

Life of this patent

Abstract

Claims20