US 5,497,263 A · Variable delay circuit and clock signal supply unit using the same

Abstract

A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units. A clock signal supply device for supplying a second clock signal to a logic circuit block, said clock signal supply device having a clock signal generator for generating a first clock signal and a reference signal and a phase adjusting means for adjusting the phase of the first clock signal phased on a phase difference between the first clock signal and the reference signal and outputting the phase-adjusted signal as a second clock signal, wherein the phase adjusting unit comprises a first variable delay circuit capable of delay operation in initial adjustment of the first clock signal, a second variable delay circuit, disposed in series with the first variable delay circuit, for performing the delay operation after the initial adjustment, and control circuits for controlling delay times of the first and second variable delay circuits.

Claims14

Dependent claims

A variable delay circuit for transferring an input signal with a variable delay which depends upon a group of binary control signals, comprising:

a plurality of selectors each provided in correspondence to and controlled by one of the binary control signals, each selector having first, second and third inputs and an output, said first and second inputs being supplied with signals to be selected by said each selector and said third input being supplied with one of the group of binary control signals, said each selector selecting one of the signals to be selected depending upon a value of the one binary control signal, said each selector supplying said output with the selected one signal;
said first input of each selector being connected to receive said input signal;
said plurality of selectors being connected in series in such a manner that the output of an i-th one of said selectors is connected to the second input of an (i - 1)-th one of said selectors, wherein i = 2, 3, . . . n, and Wherein n is the number of selectors;
wherein a first one of said selectors provides a delayed signal of the input signal to said output of said first selector with a delay time which is dependent upon a number of selectors through which the input signal passes in series until said input signal reaches said output of said first selector.

1 more element

A variable delay circuit for transferring a signal input thereto with a variable delay which depends upon values of a group of binary control signals, comprising:

a plurality of selectors each provided in correspondence to and controlled by one of the binary control signals, each selector having first, second and third inputs and an output, said first and second inputs being supplied with signals to be selected by said each selector and said third input being supplied with one of the group of binary control signals, said each selector selecting one of the signals to be selected depending upon a value of the one binary control signal, said each selector supplying said output with the selected one signal;
and
a plurality of delay circuit elements each provided in correspondence to one of said plurality of selectors and series connected with each other, a first one of said delay circuit elements being connected to receive said input signal, and an output of an i-th one of said plurality of delay circuit elements being connected to said first input of an i-th one of said selectors, wherein i = 2, 3 . . . n, and wherein n is the number of selectors and delay circuit elements;
said plurality of selectors being connected together in series in such a manner that the output of a j-th one of said selectors is connected to the second input of a (j - 1)-th one of said selectors, wherein j = 2, 3, . . . n;
wherein a first one of said selectors provides a delayed signal of the input signal to said output of said first selector with a delay time which is dependent upon a number of delay circuit elements through which the input signal passes in series until said input signal reaches said output of said first selector.

2 more elements

Dependencies are inferred from the claim text.

Variable delay circuit and clock signal supply unit using the same

Life of this patent

Variable delay circuit and clock signal supply unit using the same

Life of this patent

Abstract

Claims14