Apparatus for processing BPSK signal transmitted with NTSC TV on quadrature-phase video

A digital signal receiver for use with a system which in a combined transmission with a video carrier wave the amplitude of which is modulated in accordance with a composite video signal transmits binary phase-shift keying modulation sidebands of a suppressed carrier wave in quadrature phasing with said video carrier wave, a first bit-serial digital signal being encoded in a binary phase-shift keying signal having a prescribed phase-shift keying rate that is a multiple of a horizontal scan line rate for said composite video signal and modulating the amplitude of said suppressed carrier to generate said binary phase-shift keying modulation sidebands thereof, said combined transmission being made after vestigial-sideband filtering, said digital signal receiver comprising:

• a tuner for supplying intermediate-frequency signal response to a selected radio-frequency signal comprising an amplitude-modulated video carrier wave modulated in accordance with a composite video signal and a binary phase-shift-keyed suppressed carrier wave in quadrature phasing with said video carrier wave, said binary phase-shift-keyed suppressed carrier wave being modulated in accordance with a binary phase-shift-keying signal encoding a first bit-serial digital signal;
• an intermediate-frequency amplifier for said intermediate-frequency signal response, said intermediate-frequency amplifier including filtering and amplifying elements and supplying an amplified intermediate-frequency amplifier response;
• first controlled oscillator circuitry for generating in-phase and quadrature-phase intermediate-frequency video carrier waves, at an intermediate frequency and average phase which are controlled by a frequency and phase error signal;
• an in-phase video detector receptive of said amplified intermediate-frequency amplifier response for synchronously detecting, in accordance with said in-phase intermediate-frequency video carrier wave supplied thereto, modulation of the amplitude of said video carrier to generate an in-phase detected signal in which said composite video signal is regenerated, because of said vestigial-sideband filtering the regenerated composite video signal being accompanied by upper-frequency remnants of said binary phase-shift keying signal;
• a quadrature-phase video detector receptive of said amplified intermediate-frequency amplifier response for synchronously detecting, in accordance with said quadrature-phase intermediate-frequency video carrier wave supplied thereto, modulation of the amplitude of said video carrier to generate a quadrature-phase detected signal in which said binary phase-shift-keying signal is regenerated accompanied by said frequency and phase error signal, because of said vestigial-sideband filtering the regenerated binary phase-shift-keying signal being further accompanied by at least upper-frequency remnants of said composite video signal;
• a horizontal sync separator for separating horizontal synchronizing pulses from the composite video signal detected by said in-phase video detector;
• line-locked second controlled oscillator circuitry for generating clocking oscillations at a frequency and phase controlled by said separated horizontal synchronizing pulses, which oscillations are at a multiple of said horizontal scan line rate for said composite video signal;
• an analog-to-digital converter having an input connection for receiving said quadrature-phase detected signal as its analog input signal and having an output connection for supplying digitized response to samples of said quadrature-phase detected signal, as sampled at said prescribed phase-shift keying .rate to provide a digital quadrature-phase detected signal;
• first and second one-frame digital delays in cascade connection, said first one-frame digital delay receptive of said quadrature-phase detected signal for supplying said quadrature-phase detected signal as delayed by the duration of a frame of said composite video signal as its respective delayed response, and said second one-frame digital delay receptive of the delayed response of said first one-frame digital delay for supplying said quadrature-phase detected signal as delayed by the duration of two frames of said composite video signal as its respective delayed response;
• a first digital subtractor for differentially combining said quadrature-phase detected signal from said analog-to-digital converter and the delayed response of said first one-frame digital delay, thereby to generate a first difference signal;
• a second digital subtractor for differentially combining the delayed response of said first one-frame digital delay and the delayed response of said second one-frame digital delay, thereby to generate a second difference signal;
• means, responding to said first difference signal, for providing a first highpass line-comb filter response which includes three-level digital response to phase-shift keying symbols, with said remnants of said composite video signal being suppressed in said first highpass line-comb filter response;
• first symbol decision circuitry responsive to said first highpass line-comb filter response for deciding the identity of each phase-shift keying symbol, thereby to generate each successive bit in a second bit-serial digital signal;
• a first partial-response filter, responding to said second bit-serial digital signal, for generating a third bit-serial digital signal that substantially reproduces said first bit-serial digital signal;
• means, responding to said second difference signal, for providing a second highpass line-comb filter response which includes five-level digital response to phase-shift keying symbols, with said remnants of said composite video signal being suppressed in said second highpass line-comb filter response;
• second symbol decision circuitry responsive to said second highpass line-comb filter response for deciding the identity of each phase-shift keying symbol, thereby to generate each successive bit in a fourth bit-serial digital signal;
• a second partial-response filter, responding to said fourth bit-serial digital signal, for generating as its response a fifth bit-serial digital signal that substantially reproduces said first bit-serial digital signal;
• and
• means for selecting the successive bits of a sixth bit-serial digital signal, by selecting as the current bit of said sixth bit-serial digital signal the one of the current bits of said third and fifth bit-serial digital signals least likely to be in error owing to remnants of said composite video signal affecting symbol decision.

A digital signal receiver for use with a system which in a combined transmission with a video carrier wave the amplitude of which is modulated in accordance with a composite video signal transmits binary phase-shift keying modulation sidebands of a suppressed carrier wave in quadrature phasing with said video carrier wave, a first bit-serial digital signal being encoded in a binary phase-shift keying signal having a prescribed phase-shift keying rate that is a multiple of a horizontal scan line rate for said composite video signal and modulating the amplitude of said suppressed carrier to generate said binary phase-shift keying modulation sidebands thereof, said combined transmission being made after vestigial-sideband filtering, said digital signal receiver comprising:

• a tuner for supplying intermediate-frequency signal response to a selected radio-frequency signal comprising an amplitude-modulated video carrier wave modulated in accordance with a composite video signal and a binary phase-shift-keyed suppressed carrier wave in quadrature phasing with said video carrier wave, said binary phase-shift-keyed suppressed carrier wave being modulated in accordance with a binary phase-shift-keying signal encoding a first bit-serial digital signal;
• an intermediate-frequency amplifier for said intermediate-frequency signal response, said intermediate-frequency amplifier including filtering and amplifying elements and supplying an amplified intermediate-frequency amplifier response;
• first controlled oscillator circuitry for generating in-phase and quadrature-phase intermediate-frequency video carrier waves, at an intermediate frequency and average phase which are controlled by a frequency and phase error signal;
• an in-phase video detector receptive of said amplified intermediate-frequency amplifier response for synchronously detecting, in accordance with said in-phase intermediate-frequency video carrier wave supplied thereto, modulation of the amplitude of said video carrier to generate an in-phase detected signal in which said composite video signal is regenerated, because of said vestigial-sideband filtering the regenerated composite video signal being accompanied by upper-frequency remnants of said binary phase-shift keying signal;
• a quadrature-phase video detector receptive of said amplified intermediate-frequency amplifier response for synchronously detecting, in accordance with said quadrature-phase intermediate-frequency video carrier wave supplied thereto, modulation of the amplitude of said video carrier to generate a quadrature-phase detected signal in which said binary phase-shift-keying signal is regenerated accompanied by said frequency and phase error signal, because of said vestigial-sideband filtering the regenerated binary phase-shift-keying signal being further accompanied by at least upper-frequency remnants of said composite video signal;
• a horizontal sync separator for separating horizontal synchronizing pulses from the composite video signal detected by said in-phase video detector;
• line-locked second controlled oscillator circuitry for generating clocking oscillations at a frequency and phase controlled by said separated horizontal synchronizing pulses, which oscillations are at a multiple of said horizontal scan line rate for said composite video signal;
• an analog-to-digital converter having an input connection for receiving said quadrature-phase detected signal as its analog input signal and having an output connection for supplying digitized response to samples of said quadrature-phase detected signal, as sampled at said prescribed phase-shift keying rate to provide a digital quadrature-phase detected signal;
• first and second one-frame digital delays in cascade connection, said first one-frame digital delay receptive of said quadrature-phase detected signal for supplying said quadrature-phase detected signal as delayed by the duration of a frame of said composite video signal as its respective delayed response, and said second one-frame digital delay receptive of the delayed response of said first one-frame digital delay for supplying said quadrature-phase detected signal as delayed by the duration of two frames of said composite video signal as its respective delayed response;
• a first digital subtractor for differentially combining said quadrature-phase detected signal from said analog-to-digital converter and the delayed response of said first one-frame digital delay, thereby to generate a first difference signal;
• a second digital subtractor for differentially combining the delayed response of said first one-frame digital delay and the delayed response of said second one-frame digital delay, thereby to generate a second difference signal;
• means, responding to said first difference signal, for providing a first highpass line-comb filter response which includes three-level digital response to phase-shift keying symbols, with said remnants of said composite video signal being suppressed in said first highpass line-comb filter response;
• first symbol decision circuitry responsive to said first highpass line-comb filter response for deciding the identity of each phase-shift keying symbol, thereby to generate each successive bit in a second bit-serial digital signal;
• a first partial-response filter, responding to said second bit-serial digital signal, for generating a third bit-serial digital signal that substantially reproduces said first bit-serial digital signal;
• means, responding to said first difference signal, for providing a second highpass line-comb filter response which includes five-level digital response to phase-shift keying symbols, with said remnants of said composite video signal being suppressed in said second highpass line-comb filter response;
• second symbol decision circuitry responsive to said second highpass line-comb filter response for deciding the identity of each phase-shift keying symbol, thereby to generate each successive bit in a fourth bit-serial digital signal;
• a second partial-response filter, responding to said fourth bit-serial digital signal, for generating as its response a fifth bit-serial digital signal that substantially reproduces said first bit-serial digital signal;
• means for selecting the successive bits of a sixth bit-serial digital signal, by selecting as the current bit of said sixth bit-serial digital signal the one of the current bits of said third and fifth bit-serial digital signals least likely to be in error owing to remnants of said composite video signal affecting symbol decision;
• means, responding to said second difference signal, for providing a third highpass line-comb filter response which includes five-level digital response to phase-shift keying symbols, with said remnants of said composite video signal being suppressed in said third highpass line-comb filter response;
• third symbol decision circuitry responsive to said third highpass line-comb filter response for deciding the identity of each phase-shift keying symbol, thereby to generate each successive bit in a seventh bit-serial digital signal;
• a third partial-response filter, responding to said seventh bit-serial digital signal, for generating an eighth bit-serial digital signal;
• means, responding to said second difference signal, for providing a fourth highpass line-comb filter response which includes nine-level digital response to phase-shift keying symbols, with said remnants of said composite video signal being suppressed in said fourth highpass line-comb filter response;
• fourth symbol decision circuitry responsive to said fourth highpass line-comb filter response for deciding the identity of each phase-shift keying symbol, thereby to generate each successive bit in a ninth bit-serial digital signal;
• a fourth partial-response filter, responding to said ninth bit-serial digital signal, for generating as its response a tenth bit-serial digital signal;
• means for selecting the successive bits of an eleventh bit-serial digital signal, by selecting as the current bit of said eleventh bit-serial digital signal the one of the current bits of said eighth and tenth bit-serial digital signals least likely to be in error owing to remnants of said composite video signal affecting symbol decision;
• an exclusive-OR gate having a first input for receiving said eleventh bit-serial digital signal, having a second input, and having an output for supplying a twelfth bit-serial digital signal;
• means for selecting the successive bits of a thirteenth bit-serial digital signal, by selecting as the current bit of said thirteenth bit-serial digital signal the one of the current bits of said sixth and twelfth bit-serial digital signals least likely to be in error owing to remnants of said composite video signal affecting symbol decision;
• and
• a third one-frame digital delay receptive of said thirteenth bit-serial digital signal for supplying to the second input of said exclusive-OR gate said thirteenth bit-serial digital signal after being delayed by the duration of a frame of said composite video signal.