Sync chip clamping/sync separator circuit

A sync chip clamping/sync separation circuit comprising:

• a differential amplification circuit which comprises a final output amplification section comprising a P channel FET, with the drain terminal of said P channel FET being connected to an inverting input terminal of a previous stage differential amplification section;
• current limitation means which limits a current which pulls down the drain terminal of the P channel FET of said differential amplification circuit to a current which is less than the current which flows when said P channel FET is ON;
• voltage supply means which supplies a constant voltage to a non inverting input terminal of said differential amplification circuit;
• an input coupling capacitor which is interposed between the inverting input terminal of said differential amplification circuit and a positive polarity video signal input terminal;
• and
• sync signal output means which takes out a sync signal from an output of the previous stage differential amplification section, wherein said sync signal output means has an input connected between said output of the previous stage differential amplification section and the gate terminal of the P channel FET of said differential amplification circuit.