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US 5,497,190 AGranted
Digital to analog converter arithmetic circuit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorMasahiko Okamura
Life of this patent
Estimating the term…
Abstract
In a DAC-output circuit of a TV set, an output judging part lowers a multiplying factor of sub-data as user data come close to zero, to converge the output onto zero in accordance with the turning down of the user data.
Claims4
A DAC arithmetic circuit comprising:
- a user data part having adjustable user data;
- a sub-data part having sub-data for compensating for irregularities in characteristics of an IC;
- an output judging part which includes a sub-data correction part for modifying said sub-data to reduce a value thereof in response to a decrease in said user data when said user data is below a predetermined value, said output judging part issuing output data based on said sub-data and said user data;
- and
- an output circuit for receiving and issuing said output data.
2 more elements
A DAC arithmetic circuit comprising:
- a user data part having at least one user adjustable data value;
- a sub-data part having a preset sub-data value;
- and
- an output judging part for adding the at least one user adjustable value and the sub-data value and providing an output therefrom, wherein the output judging part includes a sub-data correction part for modifying the output judging part output when the user adjustable data value exceeds a predetermined value.
1 more element
Dependencies are inferred from the claim text.