Phase synchronization circuit and method therefor for a phase locked loop

In a phase locked loop (PLL) that generates an output frequency signal responsive to a reference frequency signal, the output frequency signal and the reference frequency signal are each characterized by frequency and phase, the output frequency signal has a higher frequency than the reference frequency signal, the frequency of the reference frequency signal is divided to produce a divided reference frequency signal, the frequency of the output frequency signal is divided to produce a feedback signal, the PLL having first and second states, a method for synchronizing the phase of the divided reference frequency signal and the phase of the feedback signal comprising the steps of:

• holding each of the divided reference frequency signal and the feedback signal in a predetermined state;
• enabling during the second state of the PLL, the divided reference frequency signal responsive to the phase of the reference frequency signal;
• determining a phase relationship between the reference frequency signal and the output frequency signal;
• and
• enabling the feedback signal responsive to enabling the divided reference frequency signal and the determined phase relationship.

In a phase locked loop (PLL) that generates an output frequency signal responsive to a reference frequency signal, the output frequency signal and the reference frequency signal are each characterized by frequency and phase, the output frequency signal has a higher frequency than the reference frequency signal, the frequency of the reference frequency signal is divided to produce a divided reference frequency signal, the frequency of the output frequency signal is divided to produce a feedback signal, a phase error is indicative of a difference between the phase of the reference frequency signal and the phase of the output frequency signal, the PLL having a first and a second state responsive to a request signal, an occurrence of the request signal is not synchronized in time with a periodic indication of the phase error, a method for synchronizing the phase of the divided reference frequency signal and the phase of the feedback signal comprising the steps of:

• detecting the request signal having first and second states corresponding to first and second states of the PLL;
• when the detected requested signal is in the first state, holding each of the divided reference frequency signal and the feedback signal in a predetermined state;
• and
• when the detected requested signal is in the second state:
• enabling the divided reference frequency signal responsive to the phase of the reference frequency signal;
• determining a phase relationship between the reference frequency signal and the output frequency signal;
• and
• enabling the feedback signal responsive to enabling the divided reference frequency signal and the determined phase relationship.

A radio frequency receiver includes a phase locked loop (PLL) frequency synthesizer operative to tune the radio frequency receiver to a radio frequency channel, the PLL frequency synthesizer includes a PLL capable of being enabled and disabled responsive to a request signal, the PLL generates an output frequency signal responsive to a reference frequency signal, the output frequency signal and the reference frequency signal are each characterized by frequency and phase, the frequency of the reference frequency signal is divided to produce a divided reference frequency signal, the output frequency signal is divided to produce a feedback signal, a phase error is indicative of a difference between the phase of the reference frequency signal and the phase of the output frequency signal, the PLL is operative to reduce the phase error responsive to a periodic indication of the phase error, an occurrence of the request signal is not synchronized in time with the periodic indication of the phase error, the radio frequency receiver comprising:

• a receiver line up coupled to receive a radio frequency signal and operative to produce a received signal;
• a processor coupled to receive the received signal and operative to produce the request signal responsive to the received signal;
• and
• a phase synchronization circuit in the PLL comprising:
• a PLL state control circuit coupled to receive the request signal, the periodic indication of the phase error, and a first reset signal, and operative to produce a set signal and a PLL state control signal;
• a signal detector coupled to receive the request signal, the output frequency signal, the reference frequency signal, and the set signal, and operative to produce second and third reset signals;
• a timing control circuit coupled to receive the second and third reset signals, and the set signal, and operative to produce first and second timing signals;
• a reset circuit coupled to receive the request signal and the first and second timing signals and operative to produce the first reset signal;
• and
• a logic circuit coupled to receive the first and second timing signals, the divided reference frequency signal, and the feedback signal, and operative to produce a synchronized divided reference frequency signal and a synchronized feedback signal.

A method of operating a radio frequency receiver including a phase locked loop (PLL) frequency synthesizer operative to tune the radio frequency receiver to a radio frequency channel, the PLL frequency synthesizer includes a PLL capable of being enabled and disabled responsive to a request signal, the PLL generates an output frequency signal responsive to a reference frequency signal, the output frequency signal has a higher frequency than the reference frequency signal, the output frequency signal and the reference frequency signal are each characterized by frequency and phase, the frequency of the reference frequency signal is divided to produce a divided reference frequency signal, the output frequency signal is divided to produce a feedback signal, a phase error is indicative of a difference between the phase of the reference frequency signal and the phase of the output frequency signal, the PLL is operative to reduce the phase error responsive to a periodic indication of the phase error, an occurrence of the request signal is not synchronized in time with the periodic indication of the phase error, a method of operating the radio frequency receiver comprising the steps of:

• receiving a radio frequency signal to produce a received signal;
• process the received signal to produce the request signal;
• operating the radio frequency receiver responsive to the request signal, wherein the step of operating the radio frequency receiver further comprises the step of;
• synchronizing the phase of the divided reference frequency signal and the phase of the feedback signal in the PLL, wherein the step of synchronizing further comprises the steps of:
• detecting the request signal having first and second states corresponding to first and second states of the PLL;
• when the detected requested signal is in the first state, holding each of the divided reference frequency signal and the feedback signal in a predetermined state;
• and
• when the detected requested signal is in the second state:
• enabling the divided reference frequency signal responsive to the phase of the reference frequency signal;
• determining a phase relationship between reference frequency signal and the output frequency signal;
• and
• enabling the feedback signal responsive to enabling the divided reference frequency signal and the determined phase relationship.

A phase locked loop (PLL) having a first and a second state responsive to a request signal, the PLL is operative to reduce a phase error responsive to a periodic indication of the phase error, an occurrence of the request signal is not synchronized in time with the periodic indication of the phase error, the PLL comprising:

• a reference divider coupled to receive a reference frequency signal and a synchronized divided reference frequency signal, and operative to produce a divided reference frequency signal;
• a phase detector coupled to receive the divided reference frequency signal and a feedback signal and operative to produce a phase error signal indicative of a phase difference between a phase of the reference frequency signal and a phase of an output frequency signal;
• a loop filter coupled to receive the phase error signal and operative to produce a filtered signal;
• a voltage controlled oscillator coupled to receive the filtered signal and a PLL state control signal, and operative to produce the output frequency signal;
• a loop divider coupled to receive the output frequency signal, a synchronized feedback signal, and the PLL state control signal, and operative to produce the feedback signal;
• and
• a phase synchronization circuit comprising:
• a PLL state control circuit coupled to receive the request signal, the periodic indication of the phase error, and a first reset signal, and operative to produce a set signal and the PLL state control signal;
• a signal detector coupled to receive the request signal, the output frequency signal, the reference frequency signal, and the set signal, and operative to produce second and third reset signals;
• a timing control circuit coupled to receive the second and third reset signals, and the set signal, and operative to produce first and second timing signals;
• a reset circuit coupled to receive the request signal and the first and second timing signals and operative to produce the first reset signal;
• and
• a logic circuit coupled to receive the first and second timing signals, the divided reference frequency signal, and the feedback signal, and operative to synchronize the divided reference frequency signal and the feedback signal to produce the synchronized divided reference frequency signal and the synchronized feedback signal for coupling to the phase detector.