Signal selector circuit and signal-generating circuit

A signal selector circuit, comprising:

• a pair of switching field effect transistors (FETs) having a depletion characteristic or depletion/enhancement combined characteristics, said FETs having coupled drain terminals for use as a signal input terminal, and source terminals not coupled together for use as signal output terminals, and gate terminals;
• circuits connected with said gate terminals of said switching FETs, said circuits exhibiting a high impedance when the gates are activated so as to drive the FETs on;
• wherein, when the gate of each switching FET is short-circuited to the source or to the drain or when the FET is driven on, the gate is connected with the source or drain via a resistance lower than the impedances of the circuits connected with the gate terminals;
• and
• a signal supply circuit comprising at least two sources connected with the input terminal of the signal selector circuit.

A signal selector circuit, comprising:

• a first switching field effect transistors (FET) (Q.sub.11) and a second switching FET (Q.sub.12), said FETs having coupled drain terminals for use as a signal input terminal, and source terminals not coupled together for use as signal output terminals, and gate terminals;
• a first impedance (R.sub.11) coupled between the gate and source of the first switching FET and a second impedance (R.sub.12) coupled between the gate and source of the second switching FET;
• and
• circuits connected with said gate terminals of said first and second switching FETs, said circuits exhibiting a high impedance when the gates are activated to drive the FETs on;
• wherein the impedances of the first and second resistances are lower than the impedances of the circuits connected with the gate terminals.