Flip-flop circuit

A flip-flop circuit comprising:

• first switch means, made up of a first conductivity type transistor, for controlling passing of input data in response to a single clock signal;
• first inverter means for inverting the data passed through said first switch means;
• second inverter means for inverting the data output from said first inverter means into inverted data and for inputting the inverted data to said first inverter means;
• second switch means, made up of a second conductivity type transistor, for controlling passing of the data output from said first inverter means in response to said single clock signal, said second conductivity type transistor being one of a P-channel and N-channel transistors, said first conductivity type transistor being the other of the P-channel and N-channel transistors;
• third switching means, made up of a said second conductivity type transistor for controlling passing of the data from said second inverter means to said first inverter means in response to said single clock signal;
• third inverter means for inverting the data passed through said second switch means;
• fourth inverter means for inverting the data output from said third inverter means into inverted data and for inputting the inverted data to said third inverter means;
• fourth switch means, made up of a said first conductivity type transistor, for controlling passing of the data from said fourth inverter means in response to said single clock signal,
• which further comprises means for inputting the data output from said fourth inverter means to said first switch means via said fourth switch means.

A flip-flop circuit comprising:

• first switch means, made up of a first transmission gate having transistors, for controlling passing of input data in response to clock signals;
• first inverter means for inverting the data passed through said first switch means;
• second inverter means for inverting the data output from said first inverter means into inverted data and for inputting the inverted data to said first inverter means;
• second switch means, made up of a second transmission gate having transistors, for controlling the passing of the data output from said first inverter means in response to the clock signals, said second transmission gate operating in a complementary manner to said first transmission gate;
• third switch means, made up of a said second transmission gate, for controlling passing of the data from said second inverter means to said first inverter means in response to the clock signals;
• third inverter means for inverting the data passed through said second switch means;
• fourth inverter means for inverting the data output from said third inverter means into inverted data and for inputting the inverted data to said third inverter means;
• fourth switch means, made up of a said first transmission gate, for controlling passing of the data from said fourth inverter means to said third inverter means in response to the clock signals;
• and
• means for inputting the data output from said fourth inverter means to said first switch means via said fourth switch means.