US 5,497,113 A · Variable-slope driver for pullup-terminated transmission lines

Abstract

A transmission line driver circuit has active pullup and pulldown N-type field-effect transistors (N-FETs). An input stage employs a group of N-FETs and a group of P-type field-effect transistors (P-FETs) both being dimensioned and configured to yield a variable-slope switching characteristic for both high-to-low and low-to-high signal transitions. In the N-FET group, one N-FET has the same threshold voltage as the pulldown N-FET, is diode-connected, and is also connected in parallel with a substantially smaller N-FET. In the P-FET group, one P-FET is connected in parallel with a substantially smaller P-FET, and receives a buffered version of the output signal. Both the larger N-FET and larger P-FET conduct for only part of the respective signal transition during which they are active, so that each edge has two distinct slopes. The driver circuit also includes a differential amplifier connected in feedback configuration with the pullup N-FET to limit the maximum transmission line voltage.

Claims15

Dependent claims

A transmission line driver circuit, comprising:

a first N-type field-effect transistor (N-FET) having a conductive channel including a source connected to ground and a drain connected to an output node (OUT) of said circuit coupled during circuit operation to a transmission line having a pull termination to a positive termination voltage supply (Vt) relative to ground;
a second N-FET having a source connected to ground and having a gate and drain connected together, said second N-FET having a threshold voltage substantially the same as a threshold voltage of said first N-FET;
a third N-FET substantially smaller than said second N-FET and having a source connected to ground, having a drain connected to both the gate and drain of said second N-FET, and having a gate connected to an input node (IN) of said circuit;
and
a fourth N-FET having a conductive channel connected between the gate of said first N-FET and said drain of said second N-FET and having a gate connected to said input node (IN)
such that during a logical LOW to HIGH transition at the input node (IN), a transition slope from logical LOW to HIGH at the output node (OUT) is steep until the threshold voltage of the first N-FET is reached and thereafter is less steep, as determined by a ratio of size between the third N-FET and the second N-FET.

3 more elements

A transmission line driver circuit, comprising:

a first N-type field-effect transistor (N-FET) having a conductive channel including a source connected to ground and a drain connected to an output node (OUT) of said circuit coupled during circuit operation to a transmission line having a pullup termination to a positive termination voltage supply (Vt) relative to ground;
a second N-FET having a source connected to ground and having a gate and drain connected together, said second N-FET having a threshold voltage substantially the same as a threshold voltage of said first N-FET;
a third N-FET substantially smaller than said second N-FET and having a source connected to ground, having a drain connected to both the gate and drain of said second N-FET, and having a gate connected to an input node (IN) of said circuit;
a fourth N-FET substantially the same size as said second N-FET and having a conductive channel connected between the gate of said first N-FET and said drain of said second N-FET and having a gate connected to said input node (IN),
a first P-type field-effect transistor (P-FET) having a source connected to a positive supply node (VDD), having a drain and having a gate coupled to said output node (OUT) through a buffer having a buffer voltage threshold;
a second P-FET substantially smaller than said first P-FET and having a source connected to said (VDD), having a drain connected to said drain of said first P-FET, and having a gate connected to an input node (IN) of said circuit;
and
a third P-FET having its conductive channel connected between the gate of said first N-FET and said drain of said first P-FET and having its gate connected to said input node (IN),
such that during a logical LOW to HIGH transistion at the input node (IN), a transition slope from logical LOW to HIGH at the output node (OUT) is steep until the threshold voltage of the first N-FET is reached and thereafter is less steep, as determined by a ratio of size between the smaller third N-FET and the second N-FET;
and, such that during a logical HIGH to LOW transition at the input node (IN), a transition slope from logical HIGH to LOW at the output node (OUT) is less steep as determined by a ratio of size between the smaller second P-FET and the first P-FET until the buffer voltage threshold is reached whereupon the first P-FET conducts and increases a slope of a control voltage at the gate of the first N-FET causing a more steep transition slope from logical HIGH to LOW at the output node (OUT).

7 more elements

A transmission line driver circuit for driving an output signal onto a transmission line connected through a termination resistance to a termination positive voltage supply (Vt) comprising:

a first n-channel field-effect transistor (N-FET) (Q2) having its conductive channel connected between ground and an output node (OUT) of said circuit which is connected to said transmission line and having its gate connected to a circuit node (A);
a second N-FET (Q7) having its conductive channel connected between said output node (OUT) and a positive supply node (VDD) and having its gate connected to a circuit node (B);
a third N-FET (Q12) having a drain connected to said node (A) and having its gate connected to an input node (IN) of said circuit;
a fourth N-FET (Q11) having its gate and drain connected to the source of said third N-FET (Q12) and having a source connected to ground, said fourth N-FET (Q11) being substantially the same size as said third N-FET (Q12) and having a threshold voltage substantially the same as that of said first N-FET (Q2);
a fifth N-FET (Q10) having its conductive channel connected between said source of said third N-FET (Q12) and ground and having its gate connected to said input node (IN), said fifth N-FET (Q10) being substantially smaller than said third and fourth N-FETs (Q11 and Q12);
a first P-type field-effect transistor (P-FET) (Q13) having a source connected to said node (A) and having its gate connected to said input node (IN);
a second P-FET (Q15) having its conductive channel connected between a drain of said first P-FET (Q13) and said node (VDD), said second P-FET (Q15) being substantially the same size as said first P-FET (Q13);
a third P-FET (Q14) having its conductive channel connected between said drain of said first P-FET (Q13) and said node (VDD) and having its gate connected to said input node (IN), said third P-FET (Q14) being substantially smaller than said first and second P-FETs (Q13 and Q15);
a first buffer (24) having an input connected to said output node (OUT) and having an output connected to the gate of said second P-FET (Q15);
an inverting logic gate (22) having a first input and having an output connected to said node (B);
a second buffer (20) having an input connected to said node (A) and an output connected to said first input of said inverting logic gate (22);
a sixth N-FET (Q18) having a drain connected to said node B and having its gate connected to said output node (OUT);
a seventh N-FET (Q17) having a drain connected to said node (VDD), having a source connected to the source of said sixth N-FET (Q18), and having a gate connected to a reference voltage node (REF) to which a reference-voltage-generating circuit is connected;
and
an eighth N-FET (Q16) having its conductive channel connected between said source of said sixth N-FET (Q18) and ground and having its gate connected to said node (VDD).

12 more elements

Dependencies are inferred from the claim text.

Variable-slope driver for pullup-terminated transmission lines

Life of this patent

Variable-slope driver for pullup-terminated transmission lines

Life of this patent

Abstract

Claims15