Multiple, selectable PLAS having shared inputs and outputs
AssigneeTexas Instruments Incorporated
InventorAndre Szczepanek
Life of this patent
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Abstract
Circuitry 10 is provided that contains two (or more) PLA matrix structures 12, 14 which share at least some outputs and are interconnected with a common output structure 18, individual input 30 and output 42, 62 structures, and an appropriate controller 28 for selecting which PLA matrix structure 12, 14 is to be employed. A common input structure 16 may be interconnected with the PLA matrix structures 12, 14 employed. The controller 28 may also be employed to power-down the PLA matrix structures not employed. The controller 28 may be static and select one matrix structure until reset, or dynamic and change as a function of some control signal.
Claims21
A state machine, comprising:
- at least two programmable logic array matrix structures, with each matrix structure having corresponding input terminals and output terminals and performing preselected logic operations;
- an output structure connected to said output terminals of said matrix structures;
- and
- a controller connected to said output structure for selecting said output terminals of one of said matrix structures to provide operational outputs for said state machine, said controller further connected to said matrix structures for selecting which matrix structure is provided power for its operation.
A state machine, comprising:
- a first programmable logic array matrix structure having first input terminals and first output terminals, said first programmable logic array for performing at least one preselected logic operation;
- a second programmable logic array matrix structure having second input terminals and second output terminals, said a second programmable logic array for performing at least one preselected logic operation;
- a first input structure connected to said first input terminals of said first matrix structure for supplying first input signals thereto;
- a second input structure connected to said second input terminals of said second matrix structure for supplying second input signals thereto;
- an output structure connected to said output terminals of said first and second matrix structures;
- and
- a controller connected to said output structure for selecting which of said first and second matrix structures provides operational outputs for said state machine, said controller further connected to said matrix structures for selecting which matrix structure is provided power for its operation.
A programmable logic array circuit, comprising:
- a first matrix structure having a plurality of first input terminals and a plurality of second output terminals,
- a second matrix structure having a plurality of second input terminals and a plurality of second output terminals and wherein a portion of the signals on said plurality of second output terminals are common with signals on said plurality of first output terminals of said first matrix structure,
- an output structure connected to said first output terminals and said second output terminals corresponding to said common outputs of said first and second matrix structures, and
- a controller connected to said matrix structures for selecting which matrix structure is provided power for its operation.
Dependencies are inferred from the claim text.